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According to NXP ESPI datasheet, the SPI clock rate is:
spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) )
Where System_Clock is the platform clock divided by 2,
DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15).
Isolating PM on the expression, we get:
PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1
Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz,
and DIV16 = 1 or DIV16 = 16. So,
PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1
or
PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1
Current spi-fsl-espi driver can't configure the HW for all
supported clock rates. It filters out clock rates for PM = 0
and PM = 1.
This patch allows all range of supported clock rates to be
configured on the ESPI controller.
Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
73aaf15849