9c92ab6191
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
355 lines
9.1 KiB
C
355 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Zheng Yang <zhengyang@rock-chips.com>
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* Yakir Yang <ykk@rock-chips.com>
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*/
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#ifndef __INNO_HDMI_H__
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#define __INNO_HDMI_H__
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#define DDC_SEGMENT_ADDR 0x30
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enum PWR_MODE {
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NORMAL,
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LOWER_PWR,
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};
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#define HDMI_SCL_RATE (100*1000)
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#define DDC_BUS_FREQ_L 0x4b
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#define DDC_BUS_FREQ_H 0x4c
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#define HDMI_SYS_CTRL 0x00
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#define m_RST_ANALOG (1 << 6)
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#define v_RST_ANALOG (0 << 6)
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#define v_NOT_RST_ANALOG (1 << 6)
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#define m_RST_DIGITAL (1 << 5)
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#define v_RST_DIGITAL (0 << 5)
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#define v_NOT_RST_DIGITAL (1 << 5)
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#define m_REG_CLK_INV (1 << 4)
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#define v_REG_CLK_NOT_INV (0 << 4)
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#define v_REG_CLK_INV (1 << 4)
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#define m_VCLK_INV (1 << 3)
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#define v_VCLK_NOT_INV (0 << 3)
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#define v_VCLK_INV (1 << 3)
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#define m_REG_CLK_SOURCE (1 << 2)
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#define v_REG_CLK_SOURCE_TMDS (0 << 2)
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#define v_REG_CLK_SOURCE_SYS (1 << 2)
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#define m_POWER (1 << 1)
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#define v_PWR_ON (0 << 1)
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#define v_PWR_OFF (1 << 1)
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#define m_INT_POL (1 << 0)
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#define v_INT_POL_HIGH 1
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#define v_INT_POL_LOW 0
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#define HDMI_VIDEO_CONTRL1 0x01
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#define m_VIDEO_INPUT_FORMAT (7 << 1)
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#define m_DE_SOURCE (1 << 0)
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#define v_VIDEO_INPUT_FORMAT(n) (n << 1)
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#define v_DE_EXTERNAL 1
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#define v_DE_INTERNAL 0
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enum {
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VIDEO_INPUT_SDR_RGB444 = 0,
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VIDEO_INPUT_DDR_RGB444 = 5,
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VIDEO_INPUT_DDR_YCBCR422 = 6
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};
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#define HDMI_VIDEO_CONTRL2 0x02
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#define m_VIDEO_OUTPUT_COLOR (3 << 6)
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#define m_VIDEO_INPUT_BITS (3 << 4)
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#define m_VIDEO_INPUT_CSP (1 << 0)
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#define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
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#define v_VIDEO_INPUT_BITS(n) (n << 4)
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#define v_VIDEO_INPUT_CSP(n) (n << 0)
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enum {
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VIDEO_INPUT_12BITS = 0,
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VIDEO_INPUT_10BITS = 1,
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VIDEO_INPUT_REVERT = 2,
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VIDEO_INPUT_8BITS = 3,
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};
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#define HDMI_VIDEO_CONTRL 0x03
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#define m_VIDEO_AUTO_CSC (1 << 7)
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#define v_VIDEO_AUTO_CSC(n) (n << 7)
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#define m_VIDEO_C0_C2_SWAP (1 << 0)
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#define v_VIDEO_C0_C2_SWAP(n) (n << 0)
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enum {
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C0_C2_CHANGE_ENABLE = 0,
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C0_C2_CHANGE_DISABLE = 1,
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AUTO_CSC_DISABLE = 0,
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AUTO_CSC_ENABLE = 1,
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};
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#define HDMI_VIDEO_CONTRL3 0x04
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#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
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#define m_SOF (1 << 3)
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#define m_COLOR_RANGE (1 << 2)
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#define m_CSC (1 << 0)
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#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
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#define v_SOF_ENABLE (0 << 3)
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#define v_SOF_DISABLE (1 << 3)
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#define v_COLOR_RANGE_FULL (1 << 2)
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#define v_COLOR_RANGE_LIMITED (0 << 2)
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#define v_CSC_ENABLE 1
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#define v_CSC_DISABLE 0
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#define HDMI_AV_MUTE 0x05
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#define m_AVMUTE_CLEAR (1 << 7)
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#define m_AVMUTE_ENABLE (1 << 6)
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#define m_AUDIO_MUTE (1 << 1)
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#define m_VIDEO_BLACK (1 << 0)
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#define v_AVMUTE_CLEAR(n) (n << 7)
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#define v_AVMUTE_ENABLE(n) (n << 6)
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#define v_AUDIO_MUTE(n) (n << 1)
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#define v_VIDEO_MUTE(n) (n << 0)
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#define HDMI_VIDEO_TIMING_CTL 0x08
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#define v_HSYNC_POLARITY(n) (n << 3)
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#define v_VSYNC_POLARITY(n) (n << 2)
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#define v_INETLACE(n) (n << 1)
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#define v_EXTERANL_VIDEO(n) (n << 0)
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#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
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#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
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#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
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#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
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#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
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#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
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#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
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#define HDMI_VIDEO_EXT_HDURATION_H 0x10
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#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
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#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
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#define HDMI_VIDEO_EXT_VBLANK 0x13
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#define HDMI_VIDEO_EXT_VDELAY 0x14
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#define HDMI_VIDEO_EXT_VDURATION 0x15
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#define HDMI_VIDEO_CSC_COEF 0x18
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#define HDMI_AUDIO_CTRL1 0x35
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enum {
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CTS_SOURCE_INTERNAL = 0,
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CTS_SOURCE_EXTERNAL = 1,
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};
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#define v_CTS_SOURCE(n) (n << 7)
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enum {
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DOWNSAMPLE_DISABLE = 0,
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DOWNSAMPLE_1_2 = 1,
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DOWNSAMPLE_1_4 = 2,
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};
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#define v_DOWN_SAMPLE(n) (n << 5)
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enum {
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AUDIO_SOURCE_IIS = 0,
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AUDIO_SOURCE_SPDIF = 1,
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};
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#define v_AUDIO_SOURCE(n) (n << 3)
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#define v_MCLK_ENABLE(n) (n << 2)
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enum {
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MCLK_128FS = 0,
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MCLK_256FS = 1,
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MCLK_384FS = 2,
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MCLK_512FS = 3,
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};
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#define v_MCLK_RATIO(n) (n)
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#define AUDIO_SAMPLE_RATE 0x37
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enum {
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AUDIO_32K = 0x3,
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AUDIO_441K = 0x0,
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AUDIO_48K = 0x2,
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AUDIO_882K = 0x8,
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AUDIO_96K = 0xa,
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AUDIO_1764K = 0xc,
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AUDIO_192K = 0xe,
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};
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#define AUDIO_I2S_MODE 0x38
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enum {
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I2S_CHANNEL_1_2 = 1,
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I2S_CHANNEL_3_4 = 3,
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I2S_CHANNEL_5_6 = 7,
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I2S_CHANNEL_7_8 = 0xf
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};
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#define v_I2S_CHANNEL(n) ((n) << 2)
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enum {
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I2S_STANDARD = 0,
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I2S_LEFT_JUSTIFIED = 1,
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I2S_RIGHT_JUSTIFIED = 2,
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};
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#define v_I2S_MODE(n) (n)
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#define AUDIO_I2S_MAP 0x39
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#define AUDIO_I2S_SWAPS_SPDIF 0x3a
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#define v_SPIDF_FREQ(n) (n)
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#define N_32K 0x1000
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#define N_441K 0x1880
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#define N_882K 0x3100
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#define N_1764K 0x6200
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#define N_48K 0x1800
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#define N_96K 0x3000
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#define N_192K 0x6000
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#define HDMI_AUDIO_CHANNEL_STATUS 0x3e
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#define m_AUDIO_STATUS_NLPCM (1 << 7)
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#define m_AUDIO_STATUS_USE (1 << 6)
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#define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
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#define m_AUDIO_STATUS_ADDITION (3 << 2)
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#define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
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#define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
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#define AUDIO_N_H 0x3f
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#define AUDIO_N_M 0x40
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#define AUDIO_N_L 0x41
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#define HDMI_AUDIO_CTS_H 0x45
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#define HDMI_AUDIO_CTS_M 0x46
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#define HDMI_AUDIO_CTS_L 0x47
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#define HDMI_DDC_CLK_L 0x4b
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#define HDMI_DDC_CLK_H 0x4c
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#define HDMI_EDID_SEGMENT_POINTER 0x4d
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#define HDMI_EDID_WORD_ADDR 0x4e
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#define HDMI_EDID_FIFO_OFFSET 0x4f
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#define HDMI_EDID_FIFO_ADDR 0x50
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#define HDMI_PACKET_SEND_MANUAL 0x9c
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#define HDMI_PACKET_SEND_AUTO 0x9d
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#define m_PACKET_GCP_EN (1 << 7)
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#define m_PACKET_MSI_EN (1 << 6)
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#define m_PACKET_SDI_EN (1 << 5)
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#define m_PACKET_VSI_EN (1 << 4)
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#define v_PACKET_GCP_EN(n) ((n & 1) << 7)
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#define v_PACKET_MSI_EN(n) ((n & 1) << 6)
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#define v_PACKET_SDI_EN(n) ((n & 1) << 5)
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#define v_PACKET_VSI_EN(n) ((n & 1) << 4)
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#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
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enum {
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INFOFRAME_VSI = 0x05,
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INFOFRAME_AVI = 0x06,
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INFOFRAME_AAI = 0x08,
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};
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#define HDMI_CONTROL_PACKET_ADDR 0xa0
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#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
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enum {
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AVI_COLOR_MODE_RGB = 0,
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AVI_COLOR_MODE_YCBCR422 = 1,
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AVI_COLOR_MODE_YCBCR444 = 2,
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AVI_COLORIMETRY_NO_DATA = 0,
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AVI_COLORIMETRY_SMPTE_170M = 1,
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AVI_COLORIMETRY_ITU709 = 2,
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AVI_COLORIMETRY_EXTENDED = 3,
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AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
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AVI_CODED_FRAME_ASPECT_4_3 = 1,
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AVI_CODED_FRAME_ASPECT_16_9 = 2,
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ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
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ACTIVE_ASPECT_RATE_4_3 = 0x09,
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ACTIVE_ASPECT_RATE_16_9 = 0x0A,
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ACTIVE_ASPECT_RATE_14_9 = 0x0B,
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};
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#define HDMI_HDCP_CTRL 0x52
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#define m_HDMI_DVI (1 << 1)
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#define v_HDMI_DVI(n) (n << 1)
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#define HDMI_INTERRUPT_MASK1 0xc0
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#define HDMI_INTERRUPT_STATUS1 0xc1
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#define m_INT_ACTIVE_VSYNC (1 << 5)
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#define m_INT_EDID_READY (1 << 2)
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#define HDMI_INTERRUPT_MASK2 0xc2
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#define HDMI_INTERRUPT_STATUS2 0xc3
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#define m_INT_HDCP_ERR (1 << 7)
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#define m_INT_BKSV_FLAG (1 << 6)
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#define m_INT_HDCP_OK (1 << 4)
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#define HDMI_STATUS 0xc8
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#define m_HOTPLUG (1 << 7)
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#define m_MASK_INT_HOTPLUG (1 << 5)
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#define m_INT_HOTPLUG (1 << 1)
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#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
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#define HDMI_COLORBAR 0xc9
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#define HDMI_PHY_SYNC 0xce
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#define HDMI_PHY_SYS_CTL 0xe0
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#define m_TMDS_CLK_SOURCE (1 << 5)
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#define v_TMDS_FROM_PLL (0 << 5)
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#define v_TMDS_FROM_GEN (1 << 5)
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#define m_PHASE_CLK (1 << 4)
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#define v_DEFAULT_PHASE (0 << 4)
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#define v_SYNC_PHASE (1 << 4)
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#define m_TMDS_CURRENT_PWR (1 << 3)
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#define v_TURN_ON_CURRENT (0 << 3)
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#define v_CAT_OFF_CURRENT (1 << 3)
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#define m_BANDGAP_PWR (1 << 2)
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#define v_BANDGAP_PWR_UP (0 << 2)
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#define v_BANDGAP_PWR_DOWN (1 << 2)
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#define m_PLL_PWR (1 << 1)
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#define v_PLL_PWR_UP (0 << 1)
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#define v_PLL_PWR_DOWN (1 << 1)
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#define m_TMDS_CHG_PWR (1 << 0)
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#define v_TMDS_CHG_PWR_UP (0 << 0)
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#define v_TMDS_CHG_PWR_DOWN (1 << 0)
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#define HDMI_PHY_CHG_PWR 0xe1
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#define v_CLK_CHG_PWR(n) ((n & 1) << 3)
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#define v_DATA_CHG_PWR(n) ((n & 7) << 0)
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#define HDMI_PHY_DRIVER 0xe2
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#define v_CLK_MAIN_DRIVER(n) (n << 4)
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#define v_DATA_MAIN_DRIVER(n) (n << 0)
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#define HDMI_PHY_PRE_EMPHASIS 0xe3
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#define v_PRE_EMPHASIS(n) ((n & 7) << 4)
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#define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
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#define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
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#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
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#define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
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#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
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#define v_FEEDBACK_DIV_HIGH(n) (n & 1)
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#define HDMI_PHY_PRE_DIV_RATIO 0xed
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#define v_PRE_DIV_RATIO(n) (n & 0x1f)
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#define HDMI_CEC_CTRL 0xd0
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#define m_ADJUST_FOR_HISENSE (1 << 6)
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#define m_REJECT_RX_BROADCAST (1 << 5)
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#define m_BUSFREETIME_ENABLE (1 << 2)
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#define m_REJECT_RX (1 << 1)
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#define m_START_TX (1 << 0)
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#define HDMI_CEC_DATA 0xd1
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#define HDMI_CEC_TX_OFFSET 0xd2
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#define HDMI_CEC_RX_OFFSET 0xd3
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#define HDMI_CEC_CLK_H 0xd4
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#define HDMI_CEC_CLK_L 0xd5
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#define HDMI_CEC_TX_LENGTH 0xd6
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#define HDMI_CEC_RX_LENGTH 0xd7
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#define HDMI_CEC_TX_INT_MASK 0xd8
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#define m_TX_DONE (1 << 3)
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#define m_TX_NOACK (1 << 2)
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#define m_TX_BROADCAST_REJ (1 << 1)
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#define m_TX_BUSNOTFREE (1 << 0)
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#define HDMI_CEC_RX_INT_MASK 0xd9
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#define m_RX_LA_ERR (1 << 4)
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#define m_RX_GLITCH (1 << 3)
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#define m_RX_DONE (1 << 0)
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#define HDMI_CEC_TX_INT 0xda
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#define HDMI_CEC_RX_INT 0xdb
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#define HDMI_CEC_BUSFREETIME_L 0xdc
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#define HDMI_CEC_BUSFREETIME_H 0xdd
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#define HDMI_CEC_LOGICADDR 0xde
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#endif /* __INNO_HDMI_H__ */
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