Robert Hancock 2d19c3fd80 net: axienet: increase default TX ring size to 128 ...

With previous changes to make the driver handle the TX ring size more
correctly, the default TX ring size of 64 appears to significantly
bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
Increasing this to 128 seems to bring performance up to near line rate and
shouldn't cause excess bufferbloat (this driver doesn't yet support modern
byte-based queue management).

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2022-01-19 11:29:14 +00:00

..

Kconfig

net: xilinx: drivers need/depend on HAS_IOMEM

2021-04-19 15:36:00 -07:00

ll_temac_main.c

ethtool: extend ringparam setting/getting API with rx_buf_len

2021-11-22 12:31:49 +00:00

ll_temac_mdio.c

net: ll_temac: Prepare indirect register access for multicast support

2019-05-23 09:33:57 -07:00

ll_temac.h

net: ll_temac: Add ethtool support for coalesce parameters

2020-02-29 21:30:43 -08:00

Makefile

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

2017-11-02 11:10:55 +01:00

xilinx_axienet_main.c

net: axienet: increase default TX ring size to 128

2022-01-19 11:29:14 +00:00

xilinx_axienet_mdio.c

net: axienet: Enable more clocks

2021-03-26 15:17:17 -07:00

xilinx_axienet.h

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2021-04-09 20:48:35 -07:00

xilinx_emaclite.c

net: xilinx: emaclite: Use platform_get_irq() to get the interrupt

2021-12-27 12:22:19 +00:00