753affba96
With current SDIO CIU clock frequency (12500000Hz) DW MMC controller fails to initialize some SD cards (which don't support slow mode). So increase SDIO CIU frequency from 12500000Hz to 50000000Hz by switching from the default divisor value (div-by-8) to the minimum possible value of the divisor (div-by-2) in HSDK platform code. Reported-by: Vineet Gupta <vgupta@synopsys.com> Tested-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*
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* ARC HSDK Platform support code
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*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/arcregs.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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#define ARC_CCM_UNUSED_ADDR 0x60000000
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static void __init hsdk_init_per_cpu(unsigned int cpu)
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{
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/*
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* By default ICCM is mapped to 0x7z while this area is used for
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* kernel virtual mappings, so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].iccm.sz)
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write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
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/*
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* By default DCCM is mapped to 0x8z while this area is used by kernel,
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* so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].dccm.sz)
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write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
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}
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#define ARC_PERIPHERAL_BASE 0xf0000000
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
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#define CREG_CORE_IF_CLK_DIV_2 0x1
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#define CGU_BASE ARC_PERIPHERAL_BASE
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#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
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#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
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#define CGU_PLL_STATUS_LOCK BIT(0)
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#define CGU_PLL_STATUS_ERR BIT(1)
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#define CGU_PLL_CTRL_1GHZ 0x3A10
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#define HSDK_PLL_LOCK_TIMEOUT 500
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#define HSDK_PLL_LOCKED() \
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!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
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#define HSDK_PLL_ERR() \
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!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
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static void __init hsdk_set_cpu_freq_1ghz(void)
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{
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u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
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/*
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* As we set cpu clock which exceeds 500MHz, the divider for the interface
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* clock must be programmed to div-by-2.
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*/
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iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
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/* Set cpu clock to 1GHz */
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iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
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while (!HSDK_PLL_LOCKED() && timeout--)
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cpu_relax();
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if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
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pr_err("Failed to setup CPU frequency to 1GHz!");
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}
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
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static void __init hsdk_init_early(void)
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{
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/*
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* PAE remapping for DMA clients does not work due to an RTL bug, so
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* CREG_PAE register must be programmed to all zeroes, otherwise it
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* will cause problems with DMA to/from peripherals even if PAE40 is
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* not used.
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*/
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/* Default is 1, which means "PAE offset = 4GByte" */
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writel_relaxed(0, (void __iomem *) CREG_PAE);
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/* Really apply settings made above */
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writel(1, (void __iomem *) CREG_PAE_UPDATE);
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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* minimum possible div-by-2.
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*/
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iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
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/*
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* Setup CPU frequency to 1GHz.
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* TODO: remove it after smart hsdk pll driver will be introduced.
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*/
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hsdk_set_cpu_freq_1ghz();
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}
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static const char *hsdk_compat[] __initconst = {
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"snps,hsdk",
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NULL,
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};
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MACHINE_START(SIMULATION, "hsdk")
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.dt_compat = hsdk_compat,
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.init_early = hsdk_init_early,
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.init_per_cpu = hsdk_init_per_cpu,
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MACHINE_END
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