5301b7a040
The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
Fixes: 1679bfef90 ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/1701520577-31163-10-git-send-email-quic_cang@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
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#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
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#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
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#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58
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#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
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#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
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#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
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#endif
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