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Sigma Designs chips use a variant of this controller with the following
differences:
- The BUSY bit in the STATUS register is inverted
- Bit 8 of the CONFIG register must be set
- The controller can generate interrupts
This patch adds support for the first two of these. It also calculates
and sets the correct clock divisor if a clk is provided. The bus
frequency is optionally speficied in the device tree node.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
75d31c2372