75eccf5ed8
According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
Test passed at gxl-s905x-p212 board.
The following published datasheets are wrong and should be updated
[1] GXBB v1.1.4
[2] GXL v0.3_20170314
Fixes:
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|---|---|---|
| .. | ||
| clk-audio-divider.c | ||
| clk-cpu.c | ||
| clk-mpll.c | ||
| clk-pll.c | ||
| clkc.h | ||
| gxbb-aoclk-32k.c | ||
| gxbb-aoclk-regmap.c | ||
| gxbb-aoclk.c | ||
| gxbb-aoclk.h | ||
| gxbb.c | ||
| gxbb.h | ||
| Kconfig | ||
| Makefile | ||
| meson8b.c | ||
| meson8b.h | ||