76922ebb02
the SDHC clock is derived from CSB with a fractional divider which can address "quarters"; the implementation multiplies CSB by 4 and divides it by the (integer) divider value a bug in the clock domain synchronisation requires that only even divider values get setup; we achieve this by - multiplying CSB by 2 only instead of 4 - registering with CCF the divider's bit field without bit0 - the divider's lowest bit remains clear as this is the reset value and later operations won't touch it this change keeps fully utilizing common clock primitives (needs no additional support logic, and avoids an excessive divider table) and satisfies the hardware's constraint of only supporting even divider values Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Anatolij Gustschin <agust@denx.de> |
||
|---|---|---|
| .. | ||
| clock-commonclk.c | ||
| Kconfig | ||
| Makefile | ||
| mpc512x_generic.c | ||
| mpc512x_shared.c | ||
| mpc512x.h | ||
| mpc5121_ads_cpld.c | ||
| mpc5121_ads.c | ||
| mpc5121_ads.h | ||
| pdm360ng.c | ||