Marc Zyngier 76e52dd01c irqchip/gic: Warn if GICv3 system registers are enabled
When using a GICv3 in compatibility (v2) mode, having GICv3 system
register access enabled is not really compliant with the architecture.

Warn if the firmware (or the hypervisor) has been lazy.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-10-09 22:16:55 +01:00
..
2015-09-26 20:54:53 -04:00
2015-09-08 16:48:55 -07:00
2015-09-04 11:35:03 -07:00
2015-09-11 16:21:12 -07:00
2015-09-27 06:45:18 -04:00
2015-09-08 14:35:59 -07:00
2015-09-03 16:41:38 -07:00
2015-09-11 16:42:39 -07:00
2015-09-08 17:22:35 -07:00
2015-09-26 20:53:15 -04:00
2015-09-08 16:33:16 -07:00
2015-09-09 11:17:33 -07:00
2015-09-25 11:16:53 -07:00
2015-09-17 21:41:02 -07:00
2015-09-09 10:55:32 -07:00
2015-09-05 19:37:31 +02:00
2015-09-18 09:28:20 -07:00
2015-09-21 12:02:27 -07:00
2015-09-26 20:56:50 -04:00
2015-09-18 09:28:20 -07:00