62a8ccf3a2
Now that the IOMMU driver has been introduced, it prevents any access from
a DMA master going through it that hasn't properly mapped the pages, and
that link is set up through the iommus property.
Unfortunately we forgot to add that property to the video engine node when
adding the IOMMU node, so now any DMA access is broken.
Fixes: b3a0a2f910c7 ("arm64: dts: allwinner: h6: Add IOMMU")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200628180804.79026-1-maxime@cerno.tech
87 lines
1.9 KiB
YAML
87 lines
1.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 Video Engine Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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compatible:
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enum:
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- allwinner,sun4i-a10-video-engine
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- allwinner,sun5i-a13-video-engine
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- allwinner,sun7i-a20-video-engine
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- allwinner,sun8i-a33-video-engine
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- allwinner,sun8i-h3-video-engine
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- allwinner,sun50i-a64-video-engine
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- allwinner,sun50i-h5-video-engine
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- allwinner,sun50i-h6-video-engine
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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- description: RAM Clock
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clock-names:
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items:
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- const: ahb
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- const: mod
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- const: ram
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resets:
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maxItems: 1
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allwinner,sram:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: Phandle to the device SRAM
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iommus:
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maxItems: 1
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memory-region:
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description:
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CMA pool to use for buffers allocation instead of the default
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CMA pool.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- allwinner,sram
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun7i-a20-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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video-codec@1c0e000 {
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compatible = "allwinner,sun7i-a20-video-engine";
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reg = <0x01c0e000 0x1000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_VE>;
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allwinner,sram = <&ve_sram 1>;
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};
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...
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