32ccd1ab09
Add the bindings for MT6795's clock controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-3-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
276 lines
7.7 KiB
C
276 lines
7.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6795_H
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#define _DT_BINDINGS_CLK_MT6795_H
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/* TOPCKGEN */
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#define CLK_TOP_ADSYS_26M 0
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#define CLK_TOP_CLKPH_MCK_O 1
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#define CLK_TOP_USB_SYSPLL_125M 2
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#define CLK_TOP_DSI0_DIG 3
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#define CLK_TOP_DSI1_DIG 4
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#define CLK_TOP_ARMCA53PLL_754M 5
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#define CLK_TOP_ARMCA53PLL_502M 6
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#define CLK_TOP_MAIN_H546M 7
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#define CLK_TOP_MAIN_H364M 8
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#define CLK_TOP_MAIN_H218P4M 9
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#define CLK_TOP_MAIN_H156M 10
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#define CLK_TOP_TVDPLL_445P5M 11
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#define CLK_TOP_TVDPLL_594M 12
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#define CLK_TOP_UNIV_624M 13
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#define CLK_TOP_UNIV_416M 14
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#define CLK_TOP_UNIV_249P6M 15
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#define CLK_TOP_UNIV_178P3M 16
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#define CLK_TOP_UNIV_48M 17
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#define CLK_TOP_CLKRTC_EXT 18
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#define CLK_TOP_CLKRTC_INT 19
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#define CLK_TOP_FPC 20
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#define CLK_TOP_HDMITXPLL_D2 21
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#define CLK_TOP_HDMITXPLL_D3 22
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#define CLK_TOP_ARMCA53PLL_D2 23
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#define CLK_TOP_ARMCA53PLL_D3 24
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#define CLK_TOP_APLL1 25
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#define CLK_TOP_APLL2 26
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#define CLK_TOP_DMPLL 27
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#define CLK_TOP_DMPLL_D2 28
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#define CLK_TOP_DMPLL_D4 29
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#define CLK_TOP_DMPLL_D8 30
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#define CLK_TOP_DMPLL_D16 31
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#define CLK_TOP_MMPLL 32
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#define CLK_TOP_MMPLL_D2 33
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#define CLK_TOP_MSDCPLL 34
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#define CLK_TOP_MSDCPLL_D2 35
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#define CLK_TOP_MSDCPLL_D4 36
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#define CLK_TOP_MSDCPLL2 37
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#define CLK_TOP_MSDCPLL2_D2 38
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#define CLK_TOP_MSDCPLL2_D4 39
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#define CLK_TOP_SYSPLL_D2 40
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#define CLK_TOP_SYSPLL1_D2 41
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#define CLK_TOP_SYSPLL1_D4 42
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#define CLK_TOP_SYSPLL1_D8 43
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#define CLK_TOP_SYSPLL1_D16 44
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#define CLK_TOP_SYSPLL_D3 45
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#define CLK_TOP_SYSPLL2_D2 46
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#define CLK_TOP_SYSPLL2_D4 47
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#define CLK_TOP_SYSPLL_D5 48
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#define CLK_TOP_SYSPLL3_D2 49
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#define CLK_TOP_SYSPLL3_D4 50
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#define CLK_TOP_SYSPLL_D7 51
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#define CLK_TOP_SYSPLL4_D2 52
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#define CLK_TOP_SYSPLL4_D4 53
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#define CLK_TOP_TVDPLL 54
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#define CLK_TOP_TVDPLL_D2 55
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#define CLK_TOP_TVDPLL_D4 56
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#define CLK_TOP_TVDPLL_D8 57
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#define CLK_TOP_TVDPLL_D16 58
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#define CLK_TOP_UNIVPLL_D2 59
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#define CLK_TOP_UNIVPLL1_D2 60
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#define CLK_TOP_UNIVPLL1_D4 61
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#define CLK_TOP_UNIVPLL1_D8 62
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#define CLK_TOP_UNIVPLL_D3 63
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#define CLK_TOP_UNIVPLL2_D2 64
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#define CLK_TOP_UNIVPLL2_D4 65
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#define CLK_TOP_UNIVPLL2_D8 66
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#define CLK_TOP_UNIVPLL_D5 67
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#define CLK_TOP_UNIVPLL3_D2 68
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#define CLK_TOP_UNIVPLL3_D4 69
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#define CLK_TOP_UNIVPLL3_D8 70
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#define CLK_TOP_UNIVPLL_D7 71
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#define CLK_TOP_UNIVPLL_D26 72
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#define CLK_TOP_UNIVPLL_D52 73
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#define CLK_TOP_VCODECPLL 74
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#define CLK_TOP_VCODECPLL_370P5 75
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#define CLK_TOP_VENCPLL 76
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#define CLK_TOP_VENCPLL_D2 77
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#define CLK_TOP_VENCPLL_D4 78
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#define CLK_TOP_AXI_SEL 79
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#define CLK_TOP_MEM_SEL 80
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#define CLK_TOP_DDRPHYCFG_SEL 81
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#define CLK_TOP_MM_SEL 82
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#define CLK_TOP_PWM_SEL 83
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#define CLK_TOP_VDEC_SEL 84
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#define CLK_TOP_VENC_SEL 85
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#define CLK_TOP_MFG_SEL 86
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#define CLK_TOP_CAMTG_SEL 87
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#define CLK_TOP_UART_SEL 88
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#define CLK_TOP_SPI_SEL 89
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#define CLK_TOP_USB20_SEL 90
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#define CLK_TOP_USB30_SEL 91
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#define CLK_TOP_MSDC50_0_H_SEL 92
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#define CLK_TOP_MSDC50_0_SEL 93
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#define CLK_TOP_MSDC30_1_SEL 94
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#define CLK_TOP_MSDC30_2_SEL 95
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#define CLK_TOP_MSDC30_3_SEL 96
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#define CLK_TOP_AUDIO_SEL 97
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#define CLK_TOP_AUD_INTBUS_SEL 98
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#define CLK_TOP_PMICSPI_SEL 99
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#define CLK_TOP_SCP_SEL 100
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#define CLK_TOP_MJC_SEL 101
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#define CLK_TOP_DPI0_SEL 102
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#define CLK_TOP_IRDA_SEL 103
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#define CLK_TOP_CCI400_SEL 104
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#define CLK_TOP_AUD_1_SEL 105
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#define CLK_TOP_AUD_2_SEL 106
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#define CLK_TOP_MEM_MFG_IN_SEL 107
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#define CLK_TOP_AXI_MFG_IN_SEL 108
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#define CLK_TOP_SCAM_SEL 109
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#define CLK_TOP_I2S0_M_SEL 110
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#define CLK_TOP_I2S1_M_SEL 111
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#define CLK_TOP_I2S2_M_SEL 112
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#define CLK_TOP_I2S3_M_SEL 113
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#define CLK_TOP_I2S3_B_SEL 114
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#define CLK_TOP_APLL1_DIV0 115
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#define CLK_TOP_APLL1_DIV1 116
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#define CLK_TOP_APLL1_DIV2 117
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#define CLK_TOP_APLL1_DIV3 118
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#define CLK_TOP_APLL1_DIV4 119
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#define CLK_TOP_APLL1_DIV5 120
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#define CLK_TOP_APLL2_DIV0 121
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#define CLK_TOP_APLL2_DIV1 122
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#define CLK_TOP_APLL2_DIV2 123
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#define CLK_TOP_APLL2_DIV3 124
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#define CLK_TOP_APLL2_DIV4 125
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#define CLK_TOP_APLL2_DIV5 126
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#define CLK_TOP_NR_CLK 127
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/* APMIXED_SYS */
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#define CLK_APMIXED_ARMCA53PLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_MSDCPLL 4
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#define CLK_APMIXED_VENCPLL 5
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#define CLK_APMIXED_TVDPLL 6
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#define CLK_APMIXED_MPLL 7
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#define CLK_APMIXED_VCODECPLL 8
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#define CLK_APMIXED_APLL1 9
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#define CLK_APMIXED_APLL2 10
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#define CLK_APMIXED_REF2USB_TX 11
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#define CLK_APMIXED_NR_CLK 12
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/* INFRA_SYS */
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#define CLK_INFRA_DBGCLK 0
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#define CLK_INFRA_SMI 1
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#define CLK_INFRA_AUDIO 2
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#define CLK_INFRA_GCE 3
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#define CLK_INFRA_L2C_SRAM 4
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#define CLK_INFRA_M4U 5
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#define CLK_INFRA_MD1MCU 6
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#define CLK_INFRA_MD1BUS 7
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#define CLK_INFRA_MD1DBB 8
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#define CLK_INFRA_DEVICE_APC 9
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#define CLK_INFRA_TRNG 10
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#define CLK_INFRA_MD1LTE 11
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#define CLK_INFRA_CPUM 12
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#define CLK_INFRA_KP 13
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#define CLK_INFRA_CA53_C0_SEL 14
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#define CLK_INFRA_CA53_C1_SEL 15
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#define CLK_INFRA_NR_CLK 16
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/* PERI_SYS */
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#define CLK_PERI_NFI 0
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#define CLK_PERI_THERM 1
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#define CLK_PERI_PWM1 2
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#define CLK_PERI_PWM2 3
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#define CLK_PERI_PWM3 4
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#define CLK_PERI_PWM4 5
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#define CLK_PERI_PWM5 6
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#define CLK_PERI_PWM6 7
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#define CLK_PERI_PWM7 8
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#define CLK_PERI_PWM 9
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#define CLK_PERI_USB0 10
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#define CLK_PERI_USB1 11
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#define CLK_PERI_AP_DMA 12
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#define CLK_PERI_MSDC30_0 13
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#define CLK_PERI_MSDC30_1 14
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#define CLK_PERI_MSDC30_2 15
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#define CLK_PERI_MSDC30_3 16
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#define CLK_PERI_NLI_ARB 17
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#define CLK_PERI_IRDA 18
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#define CLK_PERI_UART0 19
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#define CLK_PERI_UART1 20
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#define CLK_PERI_UART2 21
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#define CLK_PERI_UART3 22
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#define CLK_PERI_I2C0 23
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#define CLK_PERI_I2C1 24
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#define CLK_PERI_I2C2 25
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#define CLK_PERI_I2C3 26
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#define CLK_PERI_I2C4 27
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#define CLK_PERI_AUXADC 28
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#define CLK_PERI_SPI0 29
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#define CLK_PERI_UART0_SEL 30
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#define CLK_PERI_UART1_SEL 31
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#define CLK_PERI_UART2_SEL 32
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#define CLK_PERI_UART3_SEL 33
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#define CLK_PERI_NR_CLK 34
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/* MFG */
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#define CLK_MFG_BAXI 0
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#define CLK_MFG_BMEM 1
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#define CLK_MFG_BG3D 2
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#define CLK_MFG_B26M 3
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#define CLK_MFG_NR_CLK 4
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/* MM_SYS */
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#define CLK_MM_SMI_COMMON 0
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#define CLK_MM_SMI_LARB0 1
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#define CLK_MM_CAM_MDP 2
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#define CLK_MM_MDP_RDMA0 3
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#define CLK_MM_MDP_RDMA1 4
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#define CLK_MM_MDP_RSZ0 5
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#define CLK_MM_MDP_RSZ1 6
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#define CLK_MM_MDP_RSZ2 7
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#define CLK_MM_MDP_TDSHP0 8
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#define CLK_MM_MDP_TDSHP1 9
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#define CLK_MM_MDP_CROP 10
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#define CLK_MM_MDP_WDMA 11
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#define CLK_MM_MDP_WROT0 12
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#define CLK_MM_MDP_WROT1 13
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#define CLK_MM_FAKE_ENG 14
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#define CLK_MM_MUTEX_32K 15
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#define CLK_MM_DISP_OVL0 16
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#define CLK_MM_DISP_OVL1 17
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#define CLK_MM_DISP_RDMA0 18
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#define CLK_MM_DISP_RDMA1 19
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#define CLK_MM_DISP_RDMA2 20
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#define CLK_MM_DISP_WDMA0 21
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#define CLK_MM_DISP_WDMA1 22
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#define CLK_MM_DISP_COLOR0 23
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#define CLK_MM_DISP_COLOR1 24
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#define CLK_MM_DISP_AAL 25
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#define CLK_MM_DISP_GAMMA 26
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#define CLK_MM_DISP_UFOE 27
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#define CLK_MM_DISP_SPLIT0 28
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#define CLK_MM_DISP_SPLIT1 29
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#define CLK_MM_DISP_MERGE 30
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#define CLK_MM_DISP_OD 31
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#define CLK_MM_DISP_PWM0MM 32
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#define CLK_MM_DISP_PWM026M 33
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#define CLK_MM_DISP_PWM1MM 34
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#define CLK_MM_DISP_PWM126M 35
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#define CLK_MM_DSI0_ENGINE 36
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#define CLK_MM_DSI0_DIGITAL 37
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#define CLK_MM_DSI1_ENGINE 38
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#define CLK_MM_DSI1_DIGITAL 39
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#define CLK_MM_DPI_PIXEL 40
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#define CLK_MM_DPI_ENGINE 41
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#define CLK_MM_NR_CLK 42
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/* VDEC_SYS */
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#define CLK_VDEC_CKEN 0
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#define CLK_VDEC_LARB_CKEN 1
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#define CLK_VDEC_NR_CLK 2
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/* VENC_SYS */
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#define CLK_VENC_LARB 0
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#define CLK_VENC_VENC 1
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#define CLK_VENC_JPGENC 2
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#define CLK_VENC_JPGDEC 3
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#define CLK_VENC_NR_CLK 4
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#endif /* _DT_BINDINGS_CLK_MT6795_H */
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