1631ba1259
The Zicbom ISA-extension was ratified in november 2021 and introduces instructions for dcache invalidate, clean and flush operations. Implement cache management operations for non-coherent devices based on them. Of course not all cores will support this, so implement an alternative-based mechanism that replaces empty instructions with ones done around Zicbom instructions. As discussed in previous versions, assume the platform being coherent by default so that non-coherent devices need to get marked accordingly by firmware. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
27 lines
601 B
C
27 lines
601 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHE_H
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#define _ASM_RISCV_CACHE_H
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#endif
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/*
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* RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
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* the flat loader aligns it accordingly.
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*/
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#ifndef CONFIG_MMU
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#define ARCH_SLAB_MINALIGN 16
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#endif
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#endif /* _ASM_RISCV_CACHE_H */
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