Aniruddha Rao 7ac853ba78 arm64: tegra: Update SDMMC1/3 clock source for Tegra194
The default parent for SDMMC1/3 clock sources can provide maximum frequency
of 136MHz for SDR104 mode.
Update parent clock source for SDMMC1/SDMMC3 instances
to increase the output clock frequency to 195MHz and improve the perf.

Signed-off-by: Aniruddha Rao <anrao@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-06 15:22:39 +02:00
..
2022-03-23 18:37:22 -07:00
2022-03-09 15:12:32 +12:00
2022-03-28 17:29:53 -07:00
2022-03-24 11:58:57 -07:00
2022-03-23 18:37:22 -07:00