09d65c0267
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
26 lines
670 B
C
26 lines
670 B
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
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*/
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#ifndef __A1_PLL_CLKC_H
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#define __A1_PLL_CLKC_H
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#define CLKID_FIXED_PLL_DCO 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2_DIV 2
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#define CLKID_FCLK_DIV3_DIV 3
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#define CLKID_FCLK_DIV5_DIV 4
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#define CLKID_FCLK_DIV7_DIV 5
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#define CLKID_FCLK_DIV2 6
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#define CLKID_FCLK_DIV3 7
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#define CLKID_FCLK_DIV5 8
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#define CLKID_FCLK_DIV7 9
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#define CLKID_HIFI_PLL 10
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#endif /* __A1_PLL_CLKC_H */
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