5c99f04fec
This patch updates the driver to match the latest Realtek release, and it is an important step in getting the internal code source at Realtek to match the code in the kernel. The primary reason for this is to make it easier for Realtek to maintain the kernel source without requiring an intermediate like me. In this process of merging the two source repositories, there are a lot of changes in both, and this commit is rather large. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
120 lines
3.5 KiB
C
120 lines
3.5 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2014 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __FW_COMMON_H__
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#define __FW_COMMON_H__
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#define REG_SYS_FUNC_EN 0x0002
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#define REG_MCUFWDL 0x0080
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#define FW_8192C_START_ADDRESS 0x1000
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#define FW_8192C_PAGE_SIZE 4096
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#define FW_8723A_POLLING_TIMEOUT_COUNT 1000
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#define FW_8723B_POLLING_TIMEOUT_COUNT 6000
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#define FW_8192C_POLLING_DELAY 5
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#define MCUFWDL_RDY BIT(1)
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#define FWDL_CHKSUM_RPT BIT(2)
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#define WINTINI_RDY BIT(6)
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#define REG_RSV_CTRL 0x001C
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#define REG_HMETFR 0x01CC
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enum version_8723e {
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VERSION_TEST_UMC_CHIP_8723 = 0x0081,
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VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
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VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
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VERSION_TEST_CHIP_1T1R_8723B = 0x0106,
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VERSION_NORMAL_SMIC_CHIP_1T1R_8723B = 0x010E,
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VERSION_UNKNOWN = 0xFF,
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};
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struct rtl8723e_firmware_header {
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u16 signature;
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u8 category;
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u8 function;
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u16 version;
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u8 subversion;
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u8 rsvd1;
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u8 month;
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u8 date;
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u8 hour;
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u8 minute;
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u16 ramcodesize;
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u16 rsvd2;
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u32 svnindex;
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u32 rsvd3;
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u32 rsvd4;
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u32 rsvd5;
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};
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enum rtl8723be_cmd {
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H2C_8723BE_RSVDPAGE = 0,
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H2C_8723BE_JOINBSSRPT = 1,
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H2C_8723BE_SCAN = 2,
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H2C_8723BE_KEEP_ALIVE_CTRL = 3,
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H2C_8723BE_DISCONNECT_DECISION = 4,
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H2C_8723BE_INIT_OFFLOAD = 6,
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H2C_8723BE_AP_OFFLOAD = 8,
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H2C_8723BE_BCN_RSVDPAGE = 9,
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H2C_8723BE_PROBERSP_RSVDPAGE = 10,
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H2C_8723BE_SETPWRMODE = 0x20,
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H2C_8723BE_PS_TUNING_PARA = 0x21,
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H2C_8723BE_PS_TUNING_PARA2 = 0x22,
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H2C_8723BE_PS_LPS_PARA = 0x23,
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H2C_8723BE_P2P_PS_OFFLOAD = 0x24,
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H2C_8723BE_WO_WLAN = 0x80,
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H2C_8723BE_REMOTE_WAKE_CTRL = 0x81,
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H2C_8723BE_AOAC_GLOBAL_INFO = 0x82,
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H2C_8723BE_AOAC_RSVDPAGE = 0x83,
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H2C_8723BE_RSSI_REPORT = 0x42,
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H2C_8723BE_RA_MASK = 0x40,
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H2C_8723BE_SELECTIVE_SUSPEND_ROF_CMD,
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H2C_8723BE_P2P_PS_MODE,
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H2C_8723BE_PSD_RESULT,
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/*Not defined CTW CMD for P2P yet*/
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H2C_8723BE_P2P_PS_CTW_CMD,
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MAX_8723BE_H2CCMD
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};
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void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw);
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void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw);
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void rtl8723_enable_fw_download(struct ieee80211_hw *hw, bool enable);
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void rtl8723_fw_block_write(struct ieee80211_hw *hw,
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const u8 *buffer, u32 size);
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void rtl8723_fw_page_write(struct ieee80211_hw *hw,
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u32 page, const u8 *buffer, u32 size);
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void rtl8723_write_fw(struct ieee80211_hw *hw,
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enum version_8723e version,
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u8 *buffer, u32 size, u8 max_page);
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int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be, int count);
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int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be, int count);
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bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw,
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struct sk_buff *skb);
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void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
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#endif
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