3d21a46093
json-schema versions draft7 and earlier have a weird behavior in that any keywords combined with a '$ref' are ignored (silently). The correct form was to put a '$ref' under an 'allOf'. This behavior is now changed in the 2019-09 json-schema spec and '$ref' can be mixed with other keywords. The json-schema library doesn't yet support this, but the tooling now does a fixup for this and either way works. This has been a constant source of review comments, so let's change this treewide so everyone copies the simpler syntax. Scripted with ruamel.yaml with some manual fixups. Some minor whitespace changes from the script. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Reviewed-by: Stephen Boyd <sboyd@kernel.org> # clock Signed-off-by: Rob Herring <robh@kernel.org>
136 lines
2.8 KiB
YAML
136 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PCIe RC controller on Intel Gateway SoCs
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maintainers:
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- Dilip Kota <eswara.kota@linux.intel.com>
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properties:
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compatible:
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items:
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- const: intel,lgm-pcie
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- const: snps,dw-pcie
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device_type:
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const: pci
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"#address-cells":
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const: 3
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"#size-cells":
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const: 2
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reg:
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items:
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- description: Controller control and status registers.
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- description: PCIe configuration registers.
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- description: Controller application registers.
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: app
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ranges:
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maxItems: 1
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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reset-gpios:
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maxItems: 1
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linux,pci-domain: true
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num-lanes:
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maximum: 2
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description: Number of lanes to use for this port.
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'#interrupt-cells':
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const: 1
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interrupt-map-mask:
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description: Standard PCI IRQ mapping properties.
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interrupt-map:
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description: Standard PCI IRQ mapping properties.
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max-link-speed:
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description: Specify PCI Gen for link capability.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3, 4]
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default: 1
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bus-range:
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description: Range of bus numbers associated with this controller.
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reset-assert-ms:
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description: |
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Delay after asserting reset to the PCIe device.
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maximum: 500
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default: 100
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required:
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- compatible
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- device_type
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- "#address-cells"
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- "#size-cells"
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- reg
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- reg-names
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- ranges
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- resets
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- clocks
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- phys
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- phy-names
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- reset-gpios
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- '#interrupt-cells'
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- interrupt-map
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- interrupt-map-mask
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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pcie10: pcie@d0e00000 {
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compatible = "intel,lgm-pcie", "snps,dw-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0xd0e00000 0x1000>,
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<0xd2000000 0x800000>,
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<0xd0a41000 0x1000>;
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reg-names = "dbi", "config", "app";
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linux,pci-domain = <0>;
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max-link-speed = <4>;
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bus-range = <0x00 0x08>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &ioapic1 27 1>,
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<0 0 0 2 &ioapic1 28 1>,
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<0 0 0 3 &ioapic1 29 1>,
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<0 0 0 4 &ioapic1 30 1>;
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ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
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resets = <&rcu0 0x50 0>;
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clocks = <&cgu0 120>;
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phys = <&cb0phy0>;
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phy-names = "pcie";
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reset-assert-ms = <500>;
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reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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