Lubomir Rintel 8bea5ac0fb clk: mmp2: Fix the order of timer mux parents
Determined empirically, no documentation is available.

The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'

Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06 09:19:07 -08:00
..
2017-11-01 23:25:47 -07:00
2017-11-01 23:25:47 -07:00
2019-04-26 10:40:49 -07:00
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2019-10-17 16:36:11 +02:00