0104340a67
v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> [conor: squashed a fix from Samin to use the actual properties] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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#include "jh7110-starfive-visionfive-2.dtsi"
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/ {
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model = "StarFive VisionFive 2 v1.3B";
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compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
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};
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&gmac0 {
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starfive,tx-use-rgmii-clk;
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assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
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assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
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};
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&gmac1 {
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starfive,tx-use-rgmii-clk;
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assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
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assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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};
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&phy0 {
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-100-inverted;
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motorcomm,tx-clk-1000-inverted;
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motorcomm,rx-clk-drv-microamp = <3970>;
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motorcomm,rx-data-drv-microamp = <2910>;
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rx-internal-delay-ps = <1500>;
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tx-internal-delay-ps = <1500>;
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};
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&phy1 {
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-100-inverted;
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motorcomm,rx-clk-drv-microamp = <3970>;
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motorcomm,rx-data-drv-microamp = <2910>;
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rx-internal-delay-ps = <300>;
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tx-internal-delay-ps = <0>;
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};
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