7cf83e222b
Marvell CN10k DRAM Subsystem (DSS) supports eight event counters for monitoring performance and software can program each counter to monitor any of the defined performance event. Performance events are for interface between the DDR controller and the PHY, interface between the DDR Controller and the CHI interconnect, or within the DDR Controller. Additionally DSS also supports two fixed performance event counters, one for number of ddr reads and other for ddr writes. This patch add basic support for these performance monitoring events on CN10k. Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com> Reviewed-by: Bhaskara Budiredla <bbudiredla@marvell.com> Link: https://lore.kernel.org/r/20220211045346.17894-3-bbhushan2@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
19 lines
817 B
Makefile
19 lines
817 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o
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obj-$(CONFIG_ARM_CCN) += arm-ccn.o
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obj-$(CONFIG_ARM_CMN) += arm-cmn.o
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obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o
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obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
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obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
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obj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o
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obj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o
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obj-$(CONFIG_HISI_PMU) += hisilicon/
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obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
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obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
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obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
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obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o
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