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On SMP systems, we see a lot of spurious TX interrupts when a
program generates a steady stream of output to the pl011 UART.
The problem can be easily seen when one CPU generates the output
while another CPU handles the pl011 interrupts, and the rate of
output is low enough not to fill the TX FIFO. The problem seems
to be:
-- CPU a -- -- CPU b --
(take port lock)
pl011_start_tx
pl011_start_tx_pio
enable TXIM in REG_IMSC -> causes uart tx intr (pl011_int)
pl011_tx_chars pl011_int
...tx chars, all done... (wait for port lock)
pl011_stop_tx .
disable TXIM .
(release port lock) -> (take port lock)
check for TXIM, not enabled
(release port lock)
return IRQ_NONE
Enabling the TXIM in pl011_start_tx_pio() causes the interrupt
to be generated and delivered to CPU b, even though pl011_tx_chars()
is able to complete the TX and then disable the tx interrupt.
Fix this by enabling TXIM only after pl011_tx_chars, if it is needed.
pl011_tx_chars will return a boolean indicating whether the TX
interrupts have to be enabled.
Debugged-by: Vijaya Kumar <Vijaya.Kumar@cavium.com>
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
7d05587c9e