bb666c472c
Move the AArch64 exception injection code from EL1 to HYP, leaving only the ESR_EL1 updates to EL1. In order to come with the differences between VHE and nVHE, two set of system register accessors are provided. SPSR, ELR, PC and PSTATE are now completely handled in the hypervisor. Signed-off-by: Marc Zyngier <maz@kernel.org>
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Fault injection for both 32 and 64bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/esr.h>
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static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
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u32 esr = 0;
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vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_EL1 |
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KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
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KVM_ARM64_PENDING_EXCEPTION);
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vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
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/*
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* Build an {i,d}abort, depending on the level and the
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* instruction set. Report an external synchronous abort.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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/*
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* Here, the guest runs in AArch64 mode when in EL1. If we get
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* an AArch32 fault, it means we managed to trap an EL0 fault.
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*/
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if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
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esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
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else
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esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
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if (!is_iabt)
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esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
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vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
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}
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static void inject_undef64(struct kvm_vcpu *vcpu)
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{
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u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
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vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_EL1 |
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KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
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KVM_ARM64_PENDING_EXCEPTION);
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/*
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* Build an unknown exception, depending on the instruction
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* set.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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}
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/**
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* kvm_inject_dabt - inject a data abort into the guest
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* @vcpu: The VCPU to receive the data abort
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_dabt32(vcpu, addr);
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else
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inject_abt64(vcpu, false, addr);
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}
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/**
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* kvm_inject_pabt - inject a prefetch abort into the guest
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* @vcpu: The VCPU to receive the prefetch abort
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_pabt32(vcpu, addr);
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else
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inject_abt64(vcpu, true, addr);
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}
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/**
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* kvm_inject_undefined - inject an undefined instruction into the guest
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* @vcpu: The vCPU in which to inject the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_undef32(vcpu);
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else
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inject_undef64(vcpu);
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}
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void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
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{
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vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
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*vcpu_hcr(vcpu) |= HCR_VSE;
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}
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/**
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* kvm_inject_vabt - inject an async abort / SError into the guest
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* @vcpu: The VCPU to receive the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
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* the remaining ISS all-zeros so that this error is not interpreted as an
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* uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
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* value, so the CPU generates an imp-def value.
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*/
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void kvm_inject_vabt(struct kvm_vcpu *vcpu)
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{
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kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
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}
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