d3eabf2f2c
The CMO op macros initially used lower case, as the original iteration
of the ALT_CMO_OP alternative stringified the first parameter to
finalise the assembly for the standard variant.
As a knock-on, the T-Head versions of these CMOs had to use mixed case
defines. Commit dd23e9535889 ("RISC-V: replace cbom instructions with
an insn-def") removed the asm construction with stringify, replacing it
an insn-def macro, rending the lower-case surplus to requirements.
As far as I can tell from a brief check, CBO_zero does not see similar
use and didn't require the mixed case define in the first place.
Replace the lower case characters now for consistency with other
insn-def macros in the standard and T-Head forms, and adjust the
callsites.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20230915-aloe-dollar-994937477776@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
200 lines
5.6 KiB
C
200 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_INSN_DEF_H
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#define __ASM_INSN_DEF_H
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#include <asm/asm.h>
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#define INSN_R_FUNC7_SHIFT 25
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#define INSN_R_RS2_SHIFT 20
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#define INSN_R_RS1_SHIFT 15
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#define INSN_R_FUNC3_SHIFT 12
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#define INSN_R_RD_SHIFT 7
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#define INSN_R_OPCODE_SHIFT 0
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#define INSN_I_SIMM12_SHIFT 20
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#define INSN_I_RS1_SHIFT 15
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#define INSN_I_FUNC3_SHIFT 12
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#define INSN_I_RD_SHIFT 7
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#define INSN_I_OPCODE_SHIFT 0
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_AS_HAS_INSN
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.macro insn_r, opcode, func3, func7, rd, rs1, rs2
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.insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.insn i \opcode, \func3, \rd, \rs1, \simm12
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.endm
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#else
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#include <asm/gpr-num.h>
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.macro insn_r, opcode, func3, func7, rd, rs1, rs2
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.4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \
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(\func3 << INSN_R_FUNC3_SHIFT) | \
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(\func7 << INSN_R_FUNC7_SHIFT) | \
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(.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \
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(.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
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(.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.4byte ((\opcode << INSN_I_OPCODE_SHIFT) | \
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(\func3 << INSN_I_FUNC3_SHIFT) | \
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(.L__gpr_num_\rd << INSN_I_RD_SHIFT) | \
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(.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \
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(\simm12 << INSN_I_SIMM12_SHIFT))
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.endm
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#endif
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#define __INSN_R(...) insn_r __VA_ARGS__
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#define __INSN_I(...) insn_i __VA_ARGS__
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#else /* ! __ASSEMBLY__ */
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#ifdef CONFIG_AS_HAS_INSN
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
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#else
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#include <linux/stringify.h>
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#include <asm/gpr-num.h>
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#define DEFINE_INSN_R \
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__DEFINE_ASM_GPR_NUMS \
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" .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \
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" .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \
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" (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \
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" (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \
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" (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \
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" (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \
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" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \
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" .endm\n"
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#define DEFINE_INSN_I \
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__DEFINE_ASM_GPR_NUMS \
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" .macro insn_i, opcode, func3, rd, rs1, simm12\n" \
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" .4byte ((\\opcode << " __stringify(INSN_I_OPCODE_SHIFT) ") |" \
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" (\\func3 << " __stringify(INSN_I_FUNC3_SHIFT) ") |" \
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" (.L__gpr_num_\\rd << " __stringify(INSN_I_RD_SHIFT) ") |" \
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" (.L__gpr_num_\\rs1 << " __stringify(INSN_I_RS1_SHIFT) ") |" \
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" (\\simm12 << " __stringify(INSN_I_SIMM12_SHIFT) "))\n" \
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" .endm\n"
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#define UNDEFINE_INSN_R \
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" .purgem insn_r\n"
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#define UNDEFINE_INSN_I \
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" .purgem insn_i\n"
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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DEFINE_INSN_R \
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"insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
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UNDEFINE_INSN_R
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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DEFINE_INSN_I \
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"insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
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UNDEFINE_INSN_I
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#endif
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#endif /* ! __ASSEMBLY__ */
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#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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__INSN_R(RV_##opcode, RV_##func3, RV_##func7, \
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RV_##rd, RV_##rs1, RV_##rs2)
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#define INSN_I(opcode, func3, rd, rs1, simm12) \
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__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
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RV_##rs1, RV_##simm12)
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#define RV_OPCODE(v) __ASM_STR(v)
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#define RV_FUNC3(v) __ASM_STR(v)
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#define RV_FUNC7(v) __ASM_STR(v)
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#define RV_SIMM12(v) __ASM_STR(v)
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#define RV_RD(v) __ASM_STR(v)
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#define RV_RS1(v) __ASM_STR(v)
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#define RV_RS2(v) __ASM_STR(v)
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#define __RV_REG(v) __ASM_STR(x ## v)
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#define RV___RD(v) __RV_REG(v)
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#define RV___RS1(v) __RV_REG(v)
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#define RV___RS2(v) __RV_REG(v)
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#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
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#define RV_OPCODE_SYSTEM RV_OPCODE(115)
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#define HFENCE_VVMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define HFENCE_GVMA(gaddr, vmid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \
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__RD(0), RS1(gaddr), RS2(vmid))
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#define HLVX_HU(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \
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RD(dest), RS1(addr), __RS2(3))
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#define HLV_W(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \
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RD(dest), RS1(addr), __RS2(0))
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#ifdef CONFIG_64BIT
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#define HLV_D(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \
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RD(dest), RS1(addr), __RS2(0))
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#else
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#define HLV_D(dest, addr) \
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__ASM_STR(.error "hlv.d requires 64-bit support")
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#endif
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#define SINVAL_VMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define SFENCE_W_INVAL() \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \
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__RD(0), __RS1(0), __RS2(0))
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#define SFENCE_INVAL_IR() \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \
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__RD(0), __RS1(0), __RS2(1))
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#define HINVAL_VVMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(19), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define HINVAL_GVMA(gaddr, vmid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \
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__RD(0), RS1(gaddr), RS2(vmid))
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#define CBO_INVAL(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(0))
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#define CBO_CLEAN(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(1))
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#define CBO_FLUSH(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(2))
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#define CBO_ZERO(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(4))
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#endif /* __ASM_INSN_DEF_H */
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