55a515b1f5
Currently, sending a packet into a time gate too small for it (or always
closed) causes the queue system to hold the frame forever. Even worse,
this frame isn't subject to aging either, because for that to happen, it
needs to be scheduled for transmission in the first place. But the frame
will consume buffer memory and frame references while it is forever held
in the queue system.
Before commit a4ae997adcbd ("net: mscc: ocelot: initialize watermarks to
sane defaults"), this behavior was somewhat subtle, as the switch had a
more intricately tuned default watermark configuration out of reset,
which did not allow any single port and tc to consume the entire switch
buffer space. Nonetheless, the held frames are still there, and they
reduce the total backplane capacity of the switch.
However, after the aforementioned commit, the behavior can be very
clearly seen, since we deliberately allow each {port, tc} to consume the
entire shared buffer of the switch minus the reservations (and we
disable all reservations by default). That is to say, we allow a
permanently closed tc-taprio gate to hang the entire switch.
A careful inspection of the documentation shows that the QSYS:Q_MAX_SDU
per-port-tc registers serve 2 purposes: one is for guard band calculation
(when zero, this falls back to QSYS:PORT_MAX_SDU), and the other is to
enable oversized frame dropping (when non-zero).
Currently the QSYS:Q_MAX_SDU registers are all zero, so oversized frame
dropping is disabled. The goal of the change is to enable it seamlessly.
For that, we need to hook into the MTU change, tc-taprio change, and
port link speed change procedures, since we depend on these variables.
Frames are not dropped on egress due to a queue system oversize
condition, instead that egress port is simply excluded from the mask of
valid destination ports for the packet. If there are no destination
ports at all, the ingress counter that increments is the generic
"drop_tail" in ethtool -S.
The issue exists in various forms since the tc-taprio offload was introduced.
Fixes: de143c0e274b ("net: dsa: felix: Configure Time-Aware Scheduler via taprio offload")
Reported-by: Richie Pearn <richard.pearn@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2019 NXP
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*/
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#ifndef _MSCC_FELIX_H
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#define _MSCC_FELIX_H
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#define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
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#define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION
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#define OCELOT_PORT_MODE_INTERNAL BIT(0)
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#define OCELOT_PORT_MODE_SGMII BIT(1)
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#define OCELOT_PORT_MODE_QSGMII BIT(2)
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#define OCELOT_PORT_MODE_2500BASEX BIT(3)
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#define OCELOT_PORT_MODE_USXGMII BIT(4)
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#define OCELOT_PORT_MODE_1000BASEX BIT(5)
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/* Platform-specific information */
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struct felix_info {
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const struct resource *target_io_res;
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const struct resource *port_io_res;
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const struct resource *imdio_res;
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const struct reg_field *regfields;
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const u32 *const *map;
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const struct ocelot_ops *ops;
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const u32 *port_modes;
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int num_mact_rows;
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const struct ocelot_stat_layout *stats_layout;
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int num_ports;
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int num_tx_queues;
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struct vcap_props *vcap;
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u16 vcap_pol_base;
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u16 vcap_pol_max;
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u16 vcap_pol_base2;
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u16 vcap_pol_max2;
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const struct ptp_clock_info *ptp_caps;
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/* Some Ocelot switches are integrated into the SoC without the
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* extraction IRQ line connected to the ARM GIC. By enabling this
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* workaround, the few packets that are delivered to the CPU port
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* module (currently only PTP) are copied not only to the hardware CPU
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* port module, but also to the 802.1Q Ethernet CPU port, and polling
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* the extraction registers is triggered once the DSA tagger sees a PTP
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* frame. The Ethernet frame is only used as a notification: it is
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* dropped, and the original frame is extracted over MMIO and annotated
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* with the RX timestamp.
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*/
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bool quirk_no_xtr_irq;
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int (*mdio_bus_alloc)(struct ocelot *ocelot);
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void (*mdio_bus_free)(struct ocelot *ocelot);
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void (*phylink_validate)(struct ocelot *ocelot, int port,
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unsigned long *supported,
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struct phylink_link_state *state);
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int (*port_setup_tc)(struct dsa_switch *ds, int port,
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enum tc_setup_type type, void *type_data);
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void (*tas_guard_bands_update)(struct ocelot *ocelot, int port);
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void (*port_sched_speed_set)(struct ocelot *ocelot, int port,
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u32 speed);
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struct regmap *(*init_regmap)(struct ocelot *ocelot,
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struct resource *res);
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};
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/* Methods for initializing the hardware resources specific to a tagging
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* protocol (like the NPI port, for "ocelot" or "seville", or the VCAP TCAMs,
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* for "ocelot-8021q").
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* It is important that the resources configured here do not have side effects
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* for the other tagging protocols. If that is the case, their configuration
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* needs to go to felix_tag_proto_setup_shared().
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*/
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struct felix_tag_proto_ops {
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int (*setup)(struct dsa_switch *ds);
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void (*teardown)(struct dsa_switch *ds);
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unsigned long (*get_host_fwd_mask)(struct dsa_switch *ds);
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};
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extern const struct dsa_switch_ops felix_switch_ops;
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/* DSA glue / front-end for struct ocelot */
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struct felix {
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struct dsa_switch *ds;
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const struct felix_info *info;
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struct ocelot ocelot;
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struct mii_bus *imdio;
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struct phylink_pcs **pcs;
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resource_size_t switch_base;
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resource_size_t imdio_base;
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enum dsa_tag_protocol tag_proto;
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const struct felix_tag_proto_ops *tag_proto_ops;
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struct kthread_worker *xmit_worker;
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unsigned long host_flood_uc_mask;
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unsigned long host_flood_mc_mask;
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};
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struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port);
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int felix_netdev_to_port(struct net_device *dev);
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#endif
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