216d56c5da
This feature hands over the control of HW RC6 to the GuC. GuC decides when to put HW into RC6 based on it's internal busyness algorithms. GuCRC needs GuC submission to be enabled, and only supported on Gen12+ for now. When GuCRC is enabled, do not set HW RC6. Use a H2G message to tell GuC to enable GuCRC. When disabling RC6, tell GuC to revert RC6 control back to KMD. KMD is still responsible for enabling everything related to Coarse Power Gating though. v2: Address comments (Michal W) v3: Don't set hysterisis values when GuCRC is used (Matt Roper) v4: checkpatch() Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-15-vinay.belgaumkar@intel.com
116 lines
3.8 KiB
C
116 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2019 Intel Corporation
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*/
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#ifndef _INTEL_UC_H_
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#define _INTEL_UC_H_
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#include "intel_guc.h"
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#include "intel_guc_rc.h"
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#include "intel_guc_submission.h"
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#include "intel_guc_slpc.h"
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#include "intel_huc.h"
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#include "i915_params.h"
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struct intel_uc;
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struct intel_uc_ops {
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int (*sanitize)(struct intel_uc *uc);
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void (*init_fw)(struct intel_uc *uc);
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void (*fini_fw)(struct intel_uc *uc);
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int (*init)(struct intel_uc *uc);
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void (*fini)(struct intel_uc *uc);
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int (*init_hw)(struct intel_uc *uc);
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void (*fini_hw)(struct intel_uc *uc);
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};
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struct intel_uc {
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struct intel_uc_ops const *ops;
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struct intel_guc guc;
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struct intel_huc huc;
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/* Snapshot of GuC log from last failed load */
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struct drm_i915_gem_object *load_err_log;
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bool reset_in_progress;
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};
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void intel_uc_init_early(struct intel_uc *uc);
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void intel_uc_init_late(struct intel_uc *uc);
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void intel_uc_driver_late_release(struct intel_uc *uc);
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void intel_uc_driver_remove(struct intel_uc *uc);
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void intel_uc_init_mmio(struct intel_uc *uc);
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void intel_uc_reset_prepare(struct intel_uc *uc);
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void intel_uc_reset(struct intel_uc *uc, bool stalled);
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void intel_uc_reset_finish(struct intel_uc *uc);
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void intel_uc_cancel_requests(struct intel_uc *uc);
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void intel_uc_suspend(struct intel_uc *uc);
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void intel_uc_runtime_suspend(struct intel_uc *uc);
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int intel_uc_resume(struct intel_uc *uc);
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int intel_uc_runtime_resume(struct intel_uc *uc);
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/*
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* We need to know as early as possible if we're going to use GuC or not to
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* take the correct setup paths. Additionally, once we've started loading the
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* GuC, it is unsafe to keep executing without it because some parts of the HW,
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* a subset of which is not cleaned on GT reset, will start expecting the GuC FW
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* to be running.
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* To solve both these requirements, we commit to using the microcontrollers if
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* the relevant modparam is set and the blobs are found on the system. At this
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* stage, the only thing that can stop us from attempting to load the blobs on
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* the HW and use them is a fundamental issue (e.g. no memory for our
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* structures); if we hit such a problem during driver load we're broken even
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* without GuC, so there is no point in trying to fall back.
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*
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* Given the above, we can be in one of 4 states, with the last one implying
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* we're committed to using the microcontroller:
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* - Not supported: not available in HW and/or firmware not defined.
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* - Supported: available in HW and firmware defined.
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* - Wanted: supported + enabled in modparam.
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* - In use: wanted + firmware found on the system and successfully fetched.
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*/
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#define __uc_state_checker(x, func, state, required) \
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static inline bool intel_uc_##state##_##func(struct intel_uc *uc) \
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{ \
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return intel_##func##_is_##required(&uc->x); \
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}
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#define uc_state_checkers(x, func) \
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__uc_state_checker(x, func, supports, supported) \
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__uc_state_checker(x, func, wants, wanted) \
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__uc_state_checker(x, func, uses, used)
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uc_state_checkers(guc, guc);
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uc_state_checkers(huc, huc);
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uc_state_checkers(guc, guc_submission);
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uc_state_checkers(guc, guc_slpc);
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uc_state_checkers(guc, guc_rc);
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#undef uc_state_checkers
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#undef __uc_state_checker
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static inline int intel_uc_wait_for_idle(struct intel_uc *uc, long timeout)
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{
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return intel_guc_wait_for_idle(&uc->guc, timeout);
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}
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#define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
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static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
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{ \
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if (uc->ops->_OPS) \
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return uc->ops->_OPS(uc); \
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return _RET; \
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}
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intel_uc_ops_function(sanitize, sanitize, int, 0);
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intel_uc_ops_function(fetch_firmwares, init_fw, void, );
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intel_uc_ops_function(cleanup_firmwares, fini_fw, void, );
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intel_uc_ops_function(init, init, int, 0);
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intel_uc_ops_function(fini, fini, void, );
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intel_uc_ops_function(init_hw, init_hw, int, 0);
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intel_uc_ops_function(fini_hw, fini_hw, void, );
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#undef intel_uc_ops_function
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#endif
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