7f1abed4e9
NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate configuration values to both PHY registers. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-7-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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.. | ||
Kconfig | ||
Makefile | ||
phy-uniphier-ahci.c | ||
phy-uniphier-pcie.c | ||
phy-uniphier-usb2.c | ||
phy-uniphier-usb3hs.c | ||
phy-uniphier-usb3ss.c |