Will Deacon 7f73f7aef8 arm64: mm: report unhandled level-0 translation faults correctly
Translation faults that occur due to the input address being outside
of the address range mapped by the relevant base register are reported
as level 0 faults in ESR.DFSC.

If the faulting access cannot be resolved by the kernel (e.g. because
it is not mapped by a vma), then we report "input address range fault"
on the console. This was fine until we added support for 48-bit VAs,
which actually place PGDs at level 0 and can trigger faults for invalid
addresses that are within the range of the page tables.

This patch changes the string to report "level 0 translation fault",
which is far less confusing.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2014-11-21 14:22:22 +00:00
..
2012-09-17 13:41:58 +01:00
2014-10-09 22:26:01 -04:00
2014-10-08 05:34:24 -04:00
2013-06-07 17:58:30 +01:00