7f8faf96a2
The port scanning algorithm in devm_cxl_enumerate_ports() walks up the topology and adds cxl_port objects starting from the root down to the endpoint. When those ports are initially created they know all their dports, but they do not know the downstream cxl_port instance that represents the next descendant in the topology. Rework create_endpoint() into devm_cxl_add_endpoint() that enumerates the downstream cxl_port topology into each port's 'struct cxl_ep' record for each endpoint it that the port is an ancestor. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-7-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "cxlmem.h"
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#include "cxlpci.h"
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/**
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* DOC: cxl mem
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*
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* CXL memory endpoint devices and switches are CXL capable devices that are
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* participating in CXL.mem protocol. Their functionality builds on top of the
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* CXL.io protocol that allows enumerating and configuring components via
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* standard PCI mechanisms.
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*
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* The cxl_mem driver owns kicking off the enumeration of this CXL.mem
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* capability. With the detection of a CXL capable endpoint, the driver will
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* walk up to find the platform specific port it is connected to, and determine
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* if there are intervening switches in the path. If there are switches, a
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* secondary action is to enumerate those (implemented in cxl_core). Finally the
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* cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
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* in higher level operations.
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*/
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static void enable_suspend(void *data)
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{
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cxl_mem_active_dec();
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}
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static void remove_debugfs(void *dentry)
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{
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debugfs_remove_recursive(dentry);
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}
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static int cxl_mem_dpa_show(struct seq_file *file, void *data)
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{
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struct device *dev = file->private;
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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cxl_dpa_debug(file, cxlmd->cxlds);
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return 0;
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}
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static int cxl_mem_probe(struct device *dev)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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struct cxl_port *parent_port;
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struct cxl_dport *dport;
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struct dentry *dentry;
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int rc;
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/*
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* Someone is trying to reattach this device after it lost its port
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* connection (an endpoint port previously registered by this memdev was
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* disabled). This racy check is ok because if the port is still gone,
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* no harm done, and if the port hierarchy comes back it will re-trigger
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* this probe. Port rescan and memdev detach work share the same
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* single-threaded workqueue.
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*/
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if (work_pending(&cxlmd->detach_work))
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return -EBUSY;
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dentry = cxl_debugfs_create_dir(dev_name(dev));
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debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
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rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
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if (rc)
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return rc;
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rc = devm_cxl_enumerate_ports(cxlmd);
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if (rc)
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return rc;
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parent_port = cxl_mem_find_port(cxlmd, &dport);
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if (!parent_port) {
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dev_err(dev, "CXL port topology not found\n");
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return -ENXIO;
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}
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device_lock(&parent_port->dev);
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if (!parent_port->dev.driver) {
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dev_err(dev, "CXL port topology %s not enabled\n",
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dev_name(&parent_port->dev));
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rc = -ENXIO;
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goto unlock;
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}
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rc = devm_cxl_add_endpoint(cxlmd, dport);
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unlock:
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device_unlock(&parent_port->dev);
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put_device(&parent_port->dev);
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if (rc)
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return rc;
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/*
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* The kernel may be operating out of CXL memory on this device,
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* there is no spec defined way to determine whether this device
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* preserves contents over suspend, and there is no simple way
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* to arrange for the suspend image to avoid CXL memory which
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* would setup a circular dependency between PCI resume and save
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* state restoration.
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*
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* TODO: support suspend when all the regions this device is
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* hosting are locked and covered by the system address map,
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* i.e. platform firmware owns restoring the HDM configuration
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* that it locked.
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*/
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cxl_mem_active_inc();
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return devm_add_action_or_reset(dev, enable_suspend, NULL);
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}
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static struct cxl_driver cxl_mem_driver = {
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.name = "cxl_mem",
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.probe = cxl_mem_probe,
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.id = CXL_DEVICE_MEMORY_EXPANDER,
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};
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module_cxl_driver(cxl_mem_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(CXL);
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MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
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/*
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* create_endpoint() wants to validate port driver attach immediately after
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* endpoint registration.
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*/
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MODULE_SOFTDEP("pre: cxl_port");
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