d46392bbf5
Pull RISC-V updates from Palmer Dabbelt: - Support for cbo.zero in userspace - Support for CBOs on ACPI-based systems - A handful of improvements for the T-Head cache flushing ops - Support for software shadow call stacks - Various cleanups and fixes * tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (31 commits) RISC-V: hwprobe: Fix vDSO SIGSEGV riscv: configs: defconfig: Enable configs required for RZ/Five SoC riscv: errata: prefix T-Head mnemonics with th. riscv: put interrupt entries into .irqentry.text riscv: mm: Update the comment of CONFIG_PAGE_OFFSET riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause riscv/mm: Fix the comment for swap pte format RISC-V: clarify the QEMU workaround in ISA parser riscv: correct pt_level name via pgtable_l5/4_enabled RISC-V: Provide pgtable_l5_enabled on rv32 clocksource: timer-riscv: Increase rating of clock_event_device for Sstc clocksource: timer-riscv: Don't enable/disable timer interrupt lkdtm: Fix CFI_BACKWARD on RISC-V riscv: Use separate IRQ shadow call stacks riscv: Implement Shadow Call Stack riscv: Move global pointer loading to a macro riscv: Deduplicate IRQ stack switching riscv: VMAP_STACK overflow detection thread-safe RISC-V: cacheflush: Initialize CBO variables on ACPI systems RISC-V: ACPI: RHCT: Add function to get CBO block sizes ...
117 lines
2.3 KiB
C
117 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/scs.h>
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#include <linux/seq_file.h>
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#include <asm/sbi.h>
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#include <asm/smp.h>
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#include <asm/softirq_stack.h>
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#include <asm/stacktrace.h>
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static struct fwnode_handle *(*__get_intc_node)(void);
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void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void))
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{
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__get_intc_node = fn;
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}
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struct fwnode_handle *riscv_get_intc_hwnode(void)
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{
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if (__get_intc_node)
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return __get_intc_node();
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return NULL;
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}
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EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);
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#ifdef CONFIG_IRQ_STACKS
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#include <asm/irq_stack.h>
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DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
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#ifdef CONFIG_SHADOW_CALL_STACK
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DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
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#endif
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static void init_irq_scs(void)
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{
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int cpu;
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if (!scs_is_enabled())
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return;
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for_each_possible_cpu(cpu)
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per_cpu(irq_shadow_call_stack_ptr, cpu) =
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scs_alloc(cpu_to_node(cpu));
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}
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DEFINE_PER_CPU(ulong *, irq_stack_ptr);
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#ifdef CONFIG_VMAP_STACK
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static void init_irq_stacks(void)
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{
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int cpu;
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ulong *p;
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for_each_possible_cpu(cpu) {
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p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu));
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per_cpu(irq_stack_ptr, cpu) = p;
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}
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}
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#else
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/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
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DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack);
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static void init_irq_stacks(void)
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{
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int cpu;
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for_each_possible_cpu(cpu)
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per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu);
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}
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#endif /* CONFIG_VMAP_STACK */
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#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
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static void ___do_softirq(struct pt_regs *regs)
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{
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__do_softirq();
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}
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void do_softirq_own_stack(void)
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{
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if (on_thread_stack())
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call_on_irq_stack(NULL, ___do_softirq);
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else
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__do_softirq();
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}
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#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
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#else
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static void init_irq_scs(void) {}
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static void init_irq_stacks(void) {}
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#endif /* CONFIG_IRQ_STACKS */
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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show_ipi_stats(p, prec);
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return 0;
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}
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void __init init_IRQ(void)
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{
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init_irq_scs();
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init_irq_stacks();
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irqchip_init();
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if (!handle_arch_irq)
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panic("No interrupt controller found.");
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sbi_ipi_init();
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}
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