Matt Roper 80d6e5874a drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask
Although primary and media GuC share a single interrupt enable bit, they
each have distinct bits in the mask register.  Although we always enable
interrupts for the primary GuC before the media GuC today (and never
disable either of them), this might not always be the case in the
future, so use a RMW when updating the mask register to ensure the other
GuC's mask doesn't get clobbered.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230601215244.678611-24-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-12-19 18:34:19 -05:00
2023-11-24 09:45:40 -08:00
2023-11-26 19:48:20 -08:00
2023-11-24 09:45:40 -08:00
2023-11-04 08:07:19 -10:00
2023-11-03 09:28:53 -10:00
2023-11-03 09:48:17 -10:00
2023-11-20 09:50:09 +01:00
2023-09-07 13:52:20 -07:00
2022-10-10 12:00:45 -07:00
2023-11-26 19:59:33 -08:00

Linux kernel
============

There are several guides for kernel developers and users. These guides can
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In order to build the documentation, use ``make htmldocs`` or
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several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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