80f8ce5895
The clock COMBPHY1 has already been supported by hi3798cv200 driver, but COMBPHY0 is missing. It adds COMBPHY0 clock support. Since the mux table is being shared by COMBPHY0 and COMBPHY1, it renames comphy1_mux_p and comphy1_mux_table a bit to drop instance number '1' from there. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
377 lines
12 KiB
C
377 lines
12 KiB
C
/*
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* Hi3798CV200 Clock and Reset Generator Driver
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "crg.h"
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#include "reset.h"
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/* hi3798CV200 core CRG */
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#define HI3798CV200_INNER_CLK_OFFSET 64
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#define HI3798CV200_FIXED_24M 65
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#define HI3798CV200_FIXED_25M 66
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#define HI3798CV200_FIXED_50M 67
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#define HI3798CV200_FIXED_75M 68
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#define HI3798CV200_FIXED_100M 69
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#define HI3798CV200_FIXED_150M 70
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#define HI3798CV200_FIXED_200M 71
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#define HI3798CV200_FIXED_250M 72
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#define HI3798CV200_FIXED_300M 73
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#define HI3798CV200_FIXED_400M 74
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#define HI3798CV200_MMC_MUX 75
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#define HI3798CV200_ETH_PUB_CLK 76
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#define HI3798CV200_ETH_BUS_CLK 77
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#define HI3798CV200_ETH_BUS0_CLK 78
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#define HI3798CV200_ETH_BUS1_CLK 79
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#define HI3798CV200_COMBPHY1_MUX 80
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#define HI3798CV200_FIXED_12M 81
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#define HI3798CV200_FIXED_48M 82
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#define HI3798CV200_FIXED_60M 83
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#define HI3798CV200_FIXED_166P5M 84
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#define HI3798CV200_SDIO0_MUX 85
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#define HI3798CV200_COMBPHY0_MUX 86
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#define HI3798CV200_CRG_NR_CLKS 128
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static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
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{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
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{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
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{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
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{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
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{ HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
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{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
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{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
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{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
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{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
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};
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static const char *const mmc_mux_p[] = {
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"100m", "50m", "25m", "200m", "150m" };
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static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
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static const char *const comphy_mux_p[] = {
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"100m", "25m"};
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static u32 comphy_mux_table[] = {2, 3};
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static const char *const sdio_mux_p[] = {
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"100m", "50m", "150m", "166p5m" };
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static u32 sdio_mux_table[] = {0, 1, 2, 3};
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static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
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{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
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{ HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
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comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
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CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
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{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
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comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
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CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
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{ HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
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ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
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0x9c, 8, 2, 0, sdio_mux_table, },
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};
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static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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/* UART */
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{ HISTB_UART2_CLK, "clk_uart2", "75m",
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CLK_SET_RATE_PARENT, 0x68, 4, 0, },
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/* I2C */
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{ HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
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{ HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
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{ HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
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{ HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
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{ HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
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/* SPI */
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{ HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
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CLK_SET_RATE_PARENT, 0x70, 0, 0, },
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/* SDIO */
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{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
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CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
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{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
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CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
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/* EMMC */
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{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
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CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
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{ HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
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CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
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/* PCIE*/
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{ HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
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CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
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{ HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
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CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
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{ HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
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CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
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{ HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
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CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
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/* Ethernet */
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{ HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
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CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
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{ HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
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CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
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{ HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
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CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
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{ HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
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CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
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{ HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
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CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
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{ HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
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CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
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{ HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
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CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
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{ HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
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CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
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/* COMBPHY0 */
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{ HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",
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CLK_SET_RATE_PARENT, 0x188, 0, 0, },
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/* COMBPHY1 */
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{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
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CLK_SET_RATE_PARENT, 0x188, 8, 0, },
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/* USB2 */
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{ HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
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CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
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{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
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CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
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{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
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CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
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{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
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CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
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{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
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CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
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{ HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
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CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
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{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
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CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
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{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
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CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
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};
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static struct hisi_clock_data *hi3798cv200_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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clk_data);
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if (ret)
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goto unregister_fixed_rate;
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ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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clk_data);
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if (ret)
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goto unregister_mux;
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_gate:
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hisi_clk_unregister_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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clk_data);
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unregister_mux:
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hisi_clk_unregister_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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clk_data);
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unregister_fixed_rate:
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hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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clk_data);
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return ERR_PTR(ret);
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}
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static void hi3798cv200_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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crg->clk_data);
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hisi_clk_unregister_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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crg->clk_data);
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hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
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.register_clks = hi3798cv200_clk_register,
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.unregister_clks = hi3798cv200_clk_unregister,
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};
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/* hi3798CV200 sysctrl CRG */
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#define HI3798CV200_SYSCTRL_NR_CLKS 16
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static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
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{ HISTB_IR_CLK, "clk_ir", "24m",
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CLK_SET_RATE_PARENT, 0x48, 4, 0, },
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{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
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CLK_SET_RATE_PARENT, 0x48, 6, 0, },
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{ HISTB_UART0_CLK, "clk_uart0", "75m",
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CLK_SET_RATE_PARENT, 0x48, 10, 0, },
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};
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static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_gate:
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hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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clk_data);
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return ERR_PTR(ret);
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}
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static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
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.register_clks = hi3798cv200_sysctrl_clk_register,
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.unregister_clks = hi3798cv200_sysctrl_clk_unregister,
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};
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static const struct of_device_id hi3798cv200_crg_match_table[] = {
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{ .compatible = "hisilicon,hi3798cv200-crg",
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.data = &hi3798cv200_crg_funcs },
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{ .compatible = "hisilicon,hi3798cv200-sysctrl",
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.data = &hi3798cv200_sysctrl_funcs },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
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static int hi3798cv200_crg_probe(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg;
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crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
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if (!crg)
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return -ENOMEM;
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crg->funcs = of_device_get_match_data(&pdev->dev);
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if (!crg->funcs)
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return -ENOENT;
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crg->rstc = hisi_reset_init(pdev);
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if (!crg->rstc)
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return -ENOMEM;
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crg->clk_data = crg->funcs->register_clks(pdev);
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if (IS_ERR(crg->clk_data)) {
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hisi_reset_exit(crg->rstc);
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return PTR_ERR(crg->clk_data);
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}
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platform_set_drvdata(pdev, crg);
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return 0;
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}
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static int hi3798cv200_crg_remove(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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hisi_reset_exit(crg->rstc);
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crg->funcs->unregister_clks(pdev);
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return 0;
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}
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static struct platform_driver hi3798cv200_crg_driver = {
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.probe = hi3798cv200_crg_probe,
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.remove = hi3798cv200_crg_remove,
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.driver = {
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.name = "hi3798cv200-crg",
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.of_match_table = hi3798cv200_crg_match_table,
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},
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};
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static int __init hi3798cv200_crg_init(void)
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{
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return platform_driver_register(&hi3798cv200_crg_driver);
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}
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core_initcall(hi3798cv200_crg_init);
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static void __exit hi3798cv200_crg_exit(void)
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{
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platform_driver_unregister(&hi3798cv200_crg_driver);
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}
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module_exit(hi3798cv200_crg_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
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