3b47746cd7
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1634812857-10676-2-git-send-email-okukatla@codeaurora.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
67 lines
1.4 KiB
YAML
67 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
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maintainers:
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- Sibi Sankar <sibis@codeaurora.org>
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description:
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L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
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The OSM L3 interconnect provider aggregates the L3 bandwidth requests
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from CPU/GPU and relays it to the OSM.
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properties:
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compatible:
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enum:
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- qcom,sc7180-osm-l3
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- qcom,sc7280-epss-l3
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- qcom,sc8180x-osm-l3
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- qcom,sdm845-osm-l3
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- qcom,sm8150-osm-l3
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- qcom,sm8250-epss-l3
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reg:
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maxItems: 1
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clocks:
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items:
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- description: xo clock
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- description: alternate clock
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clock-names:
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items:
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- const: xo
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- const: alternate
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'#interconnect-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#interconnect-cells'
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additionalProperties: false
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examples:
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- |
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#define GPLL0 165
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#define RPMH_CXO_CLK 0
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osm_l3: interconnect@17d41000 {
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compatible = "qcom,sdm845-osm-l3";
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reg = <0x17d41000 0x1400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <1>;
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};
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