Ziyuan Xu 82f4b67f01 clk: rockchip: fix wrong mmc sample phase shift for rk3328
mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-10-11 14:36:01 +02:00
..
2018-07-06 11:12:20 -07:00
2018-08-23 13:44:43 -07:00
2017-11-03 09:02:30 -07:00
2018-07-09 13:49:31 +02:00
2017-11-01 23:25:43 -07:00
2018-07-06 13:52:57 -07:00
2018-08-23 13:52:46 -07:00
2018-03-16 15:53:30 -07:00
2018-06-12 16:19:22 -07:00
2018-06-12 16:19:22 -07:00
2016-03-02 17:48:26 -08:00
2018-07-06 13:44:06 -07:00
2016-10-23 10:18:45 -07:00
2017-11-01 23:25:51 -07:00
2017-11-01 23:25:51 -07:00
2018-07-06 13:44:06 -07:00