bfb5ef2219
These callbacks can be called again by the cpufreq core after the driver
is initialized and must be kept around. We currently get section
mismatch build warnings.
Don't mark them with __init.
Fixes: dcfce7c2ce ("cpufreq: sparc: Don't allocate cpufreq_driver dynamically")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
354 lines
8.3 KiB
C
354 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support
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*
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* Copyright (C) 2003 David S. Miller (davem@redhat.com)
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*
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* Many thanks to Dominik Brodowski for fixing up the cpufreq
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* infrastructure in order to make this driver easier to implement.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/cpufreq.h>
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#include <linux/threads.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/asi.h>
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#include <asm/timer.h>
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struct us2e_freq_percpu_info {
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struct cpufreq_frequency_table table[6];
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};
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/* Indexed by cpu number. */
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static struct us2e_freq_percpu_info *us2e_freq_table;
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#define HBIRD_MEM_CNTL0_ADDR 0x1fe0000f010UL
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#define HBIRD_ESTAR_MODE_ADDR 0x1fe0000f080UL
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/* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8. These are controlled
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* in the ESTAR mode control register.
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*/
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#define ESTAR_MODE_DIV_1 0x0000000000000000UL
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#define ESTAR_MODE_DIV_2 0x0000000000000001UL
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#define ESTAR_MODE_DIV_4 0x0000000000000003UL
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#define ESTAR_MODE_DIV_6 0x0000000000000002UL
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#define ESTAR_MODE_DIV_8 0x0000000000000004UL
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#define ESTAR_MODE_DIV_MASK 0x0000000000000007UL
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#define MCTRL0_SREFRESH_ENAB 0x0000000000010000UL
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#define MCTRL0_REFR_COUNT_MASK 0x0000000000007f00UL
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#define MCTRL0_REFR_COUNT_SHIFT 8
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#define MCTRL0_REFR_INTERVAL 7800
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#define MCTRL0_REFR_CLKS_P_CNT 64
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static unsigned long read_hbreg(unsigned long addr)
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{
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unsigned long ret;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=&r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static void write_hbreg(unsigned long addr, unsigned long val)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
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: "memory");
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if (addr == HBIRD_ESTAR_MODE_ADDR) {
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/* Need to wait 16 clock cycles for the PLL to lock. */
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udelay(1);
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}
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}
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static void self_refresh_ctl(int enable)
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{
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unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
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if (enable)
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mctrl |= MCTRL0_SREFRESH_ENAB;
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else
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mctrl &= ~MCTRL0_SREFRESH_ENAB;
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write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
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(void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);
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}
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static void frob_mem_refresh(int cpu_slowing_down,
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unsigned long clock_tick,
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unsigned long old_divisor, unsigned long divisor)
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{
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unsigned long old_refr_count, refr_count, mctrl;
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refr_count = (clock_tick * MCTRL0_REFR_INTERVAL);
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refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);
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mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
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old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK)
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>> MCTRL0_REFR_COUNT_SHIFT;
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mctrl &= ~MCTRL0_REFR_COUNT_MASK;
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mctrl |= refr_count << MCTRL0_REFR_COUNT_SHIFT;
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write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
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mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
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if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) {
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unsigned long usecs;
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/* We have to wait for both refresh counts (old
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* and new) to go to zero.
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*/
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usecs = (MCTRL0_REFR_CLKS_P_CNT *
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(refr_count + old_refr_count) *
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1000000UL *
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old_divisor) / clock_tick;
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udelay(usecs + 1UL);
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}
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}
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static void us2e_transition(unsigned long estar, unsigned long new_bits,
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unsigned long clock_tick,
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unsigned long old_divisor, unsigned long divisor)
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{
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estar &= ~ESTAR_MODE_DIV_MASK;
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/* This is based upon the state transition diagram in the IIe manual. */
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if (old_divisor == 2 && divisor == 1) {
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self_refresh_ctl(0);
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write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
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frob_mem_refresh(0, clock_tick, old_divisor, divisor);
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} else if (old_divisor == 1 && divisor == 2) {
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frob_mem_refresh(1, clock_tick, old_divisor, divisor);
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write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
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self_refresh_ctl(1);
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} else if (old_divisor == 1 && divisor > 2) {
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us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
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1, 2);
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us2e_transition(estar, new_bits, clock_tick,
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2, divisor);
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} else if (old_divisor > 2 && divisor == 1) {
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us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
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old_divisor, 2);
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us2e_transition(estar, new_bits, clock_tick,
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2, divisor);
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} else if (old_divisor < divisor) {
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frob_mem_refresh(0, clock_tick, old_divisor, divisor);
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write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
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} else if (old_divisor > divisor) {
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write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
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frob_mem_refresh(1, clock_tick, old_divisor, divisor);
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} else {
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BUG();
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}
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}
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static unsigned long index_to_estar_mode(unsigned int index)
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{
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switch (index) {
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case 0:
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return ESTAR_MODE_DIV_1;
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case 1:
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return ESTAR_MODE_DIV_2;
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case 2:
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return ESTAR_MODE_DIV_4;
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case 3:
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return ESTAR_MODE_DIV_6;
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case 4:
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return ESTAR_MODE_DIV_8;
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default:
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BUG();
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}
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}
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static unsigned long index_to_divisor(unsigned int index)
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{
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switch (index) {
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case 0:
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return 1;
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case 1:
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return 2;
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case 2:
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return 4;
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case 3:
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return 6;
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case 4:
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return 8;
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default:
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BUG();
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}
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}
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static unsigned long estar_to_divisor(unsigned long estar)
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{
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unsigned long ret;
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switch (estar & ESTAR_MODE_DIV_MASK) {
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case ESTAR_MODE_DIV_1:
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ret = 1;
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break;
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case ESTAR_MODE_DIV_2:
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ret = 2;
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break;
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case ESTAR_MODE_DIV_4:
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ret = 4;
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break;
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case ESTAR_MODE_DIV_6:
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ret = 6;
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break;
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case ESTAR_MODE_DIV_8:
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ret = 8;
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break;
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default:
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BUG();
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}
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return ret;
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}
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static void __us2e_freq_get(void *arg)
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{
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unsigned long *estar = arg;
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*estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
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}
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static unsigned int us2e_freq_get(unsigned int cpu)
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{
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unsigned long clock_tick, estar;
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clock_tick = sparc64_get_clock_tick(cpu) / 1000;
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if (smp_call_function_single(cpu, __us2e_freq_get, &estar, 1))
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return 0;
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return clock_tick / estar_to_divisor(estar);
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}
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static void __us2e_freq_target(void *arg)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int *index = arg;
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unsigned long new_bits, new_freq;
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unsigned long clock_tick, divisor, old_divisor, estar;
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new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000;
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new_bits = index_to_estar_mode(*index);
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divisor = index_to_divisor(*index);
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new_freq /= divisor;
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estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
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old_divisor = estar_to_divisor(estar);
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if (old_divisor != divisor) {
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us2e_transition(estar, new_bits, clock_tick * 1000,
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old_divisor, divisor);
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}
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}
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static int us2e_freq_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned int cpu = policy->cpu;
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return smp_call_function_single(cpu, __us2e_freq_target, &index, 1);
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}
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static int us2e_freq_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned int cpu = policy->cpu;
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unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
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struct cpufreq_frequency_table *table =
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&us2e_freq_table[cpu].table[0];
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table[0].driver_data = 0;
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table[0].frequency = clock_tick / 1;
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table[1].driver_data = 1;
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table[1].frequency = clock_tick / 2;
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table[2].driver_data = 2;
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table[2].frequency = clock_tick / 4;
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table[2].driver_data = 3;
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table[2].frequency = clock_tick / 6;
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table[2].driver_data = 4;
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table[2].frequency = clock_tick / 8;
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table[2].driver_data = 5;
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table[3].frequency = CPUFREQ_TABLE_END;
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policy->cpuinfo.transition_latency = 0;
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policy->cur = clock_tick;
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policy->freq_table = table;
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return 0;
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}
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static int us2e_freq_cpu_exit(struct cpufreq_policy *policy)
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{
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us2e_freq_target(policy, 0);
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return 0;
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}
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static struct cpufreq_driver cpufreq_us2e_driver = {
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.name = "UltraSPARC-IIe",
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.init = us2e_freq_cpu_init,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = us2e_freq_target,
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.get = us2e_freq_get,
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.exit = us2e_freq_cpu_exit,
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};
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static int __init us2e_freq_init(void)
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{
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unsigned long manuf, impl, ver;
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int ret;
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if (tlb_type != spitfire)
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return -ENODEV;
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__asm__("rdpr %%ver, %0" : "=r" (ver));
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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if (manuf == 0x17 && impl == 0x13) {
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us2e_freq_table = kzalloc(NR_CPUS * sizeof(*us2e_freq_table),
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GFP_KERNEL);
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if (!us2e_freq_table)
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return -ENOMEM;
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ret = cpufreq_register_driver(&cpufreq_us2e_driver);
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if (ret)
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kfree(us2e_freq_table);
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return ret;
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}
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return -ENODEV;
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}
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static void __exit us2e_freq_exit(void)
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{
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cpufreq_unregister_driver(&cpufreq_us2e_driver);
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kfree(us2e_freq_table);
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}
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MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
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MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe");
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MODULE_LICENSE("GPL");
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module_init(us2e_freq_init);
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module_exit(us2e_freq_exit);
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