8450813136
The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC: the CSRs layout is absolutely different and it doesn't support IRQs unlike DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there is no any reason to have these controllers described in the same bindings. Let's split the DT-schema up. Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW uMCTL2 DDR controller only, we need to accordingly fix the device descriptions. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220910194237.10142-15-Sergey.Semin@baikalelectronics.ru
39 lines
872 B
YAML
39 lines
872 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Zynq A05 DDR Memory Controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Manish Narani <manish.narani@xilinx.com>
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- Michal Simek <michal.simek@xilinx.com>
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description:
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The Zynq DDR ECC controller has an optional ECC support in half-bus width
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(16-bit) configuration. It is cappable of correcting single bit ECC errors
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and detecting double bit ECC errors.
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properties:
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compatible:
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const: xlnx,zynq-ddrc-a05
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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memory-controller@f8006000 {
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compatible = "xlnx,zynq-ddrc-a05";
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reg = <0xf8006000 0x1000>;
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};
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...
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