Lendacky, Thomas 853eb16b8b amd-xgbe: Base queue fifo size and enablement on ring count
When setting the fifo sizes for the queues and enabling the queues
use the number of active Tx and Rx queues that have been enabled
not the maximum number available.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-30 18:46:52 -07:00
..
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