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linux/drivers/clk/at91
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Marcin Ziemianowicz a982e45dc1 clk: at91: PLL recalc_rate() now using cached MUL and DIV values 
When a USB device is connected to the USB host port on the SAM9N12 then
you get "-62" error which seems to indicate USB replies from the device
are timing out. Based on a logic sniffer, I saw the USB bus was running
at half speed.

The PLL code uses cached MUL and DIV values which get set in set_rate()
and applied in prepare(), but the recalc_rate() function instead
queries the hardware instead of using these cached values. Therefore,
if recalc_rate() is called between a set_rate() and prepare(), the
wrong frequency is calculated and later the USB clock divider for the
SAM9N12 SOC will be configured for an incorrect clock.

In my case, the PLL hardware was set to 96 Mhz before the OHCI
driver loads, and therefore the usb clock divider was being set
to /2 even though the OHCI driver set the PLL to 48 Mhz.

As an alternative explanation, I noticed this was fixed in the past by
87e2ed338f ("clk: at91: fix recalc_rate implementation of PLL
driver") but the bug was later re-introduced by 1bdf02326b ("clk:
at91: make use of syscon/regmap internally").

Fixes: 1bdf02326b ("clk: at91: make use of syscon/regmap internally)
Cc: <stable@vger.kernel.org>
Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15 23:38:31 -07:00
..
clk-audio-pll.c clk: at91: add audio pll clock drivers 2017-09-01 15:46:52 -07:00
clk-generated.c clk: at91: clk-generated: make gclk determine audio_pll rate 2017-09-01 15:46:54 -07:00
clk-h32mx.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-main.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-master.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-peripheral.c clk: at91: Add sama5d2 suspend/resume 2017-06-29 18:47:35 -07:00
clk-pll.c clk: at91: PLL recalc_rate() now using cached MUL and DIV values 2018-05-15 23:38:31 -07:00
clk-plldiv.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-programmable.c clk: at91: pmc: Support backup for programmable clocks 2017-12-21 16:34:06 -08:00
clk-slow.c clk: at91: move slow clock controller clocks to sckc.c 2016-09-20 17:02:38 -07:00
clk-smd.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-system.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-usb.c clk: at91: Migrate to clk_hw based registration and OF APIs 2016-09-14 17:40:31 -07:00
clk-utmi.c clk: at91: utmi: set the mainck rate 2017-11-01 23:39:49 -07:00
Makefile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
pmc.c clk: at91: pmc: Support backup for programmable clocks 2017-12-21 16:34:06 -08:00
pmc.h clk: at91: pmc: Support backup for programmable clocks 2017-12-21 16:34:06 -08:00
sckc.c clk: at91: sckc: optimize boot time 2016-09-20 17:03:04 -07:00