e92f469b07
The vector register belongs to the signal context. They need to be stored
and restored as entering and leaving the signal handler. According to the
V-extension specification, the maximum length of the vector registers can
be 2^16. Hence, if userspace refers to the MINSIGSTKSZ to create a
sigframe, it may not be enough. To resolve this problem, this patch refers
to the commit 94b07c1f8c
("arm64: signal: Report signal frame size to userspace via auxv") to enable
userspace to know the minimum required sigframe size through the auxiliary
vector and use it to allocate enough memory for signal context.
Note that auxv always reports size of the sigframe as if V exists for
all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The
reason is that users usually reference this value to allocate an
alternative signal stack, and the user may use V anytime. So the user
must reserve a space for V-context in sigframe in case that the signal
handler invokes after the kernel allocating V.
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230605110724.21391-16-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _UAPI_ASM_RISCV_AUXVEC_H
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#define _UAPI_ASM_RISCV_AUXVEC_H
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/* vDSO location */
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#define AT_SYSINFO_EHDR 33
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/*
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* The set of entries below represent more extensive information
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* about the caches, in the form of two entry per cache type,
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* one entry containing the cache size in bytes, and the other
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* containing the cache line size in bytes in the bottom 16 bits
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* and the cache associativity in the next 16 bits.
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*
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* The associativity is such that if N is the 16-bit value, the
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* cache is N way set associative. A value if 0xffff means fully
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* associative, a value of 1 means directly mapped.
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*
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* For all these fields, a value of 0 means that the information
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* is not known.
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*/
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#define AT_L1I_CACHESIZE 40
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#define AT_L1I_CACHEGEOMETRY 41
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#define AT_L1D_CACHESIZE 42
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#define AT_L1D_CACHEGEOMETRY 43
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#define AT_L2_CACHESIZE 44
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#define AT_L2_CACHEGEOMETRY 45
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#define AT_L3_CACHESIZE 46
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#define AT_L3_CACHEGEOMETRY 47
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/* entries in ARCH_DLINFO */
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#define AT_VECTOR_SIZE_ARCH 9
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#define AT_MINSIGSTKSZ 51
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#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
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