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867432bec1
linux/arch/riscv
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Alexandre Ghiti 867432bec1
Revert "riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED" 
This reverts commit 9b79878ced.

The removal of this config exposes CONFIG_PHYS_RAM_BASE for all kernel
types: this value being implementation-specific, this breaks the
genericity of the RISC-V kernel so revert it.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Tested-by: Emil Renner Berthing <kernel@esmil.dk>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-06 22:41:39 -07:00
..
boot riscv: dts: fix memory size for the SiFive HiFive Unmatched 2021-08-03 21:15:31 -07:00
configs RISC-V: Enable Microchip PolarFire ICICLE SoC 2021-04-26 08:31:32 -07:00
errata riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled 2021-06-01 21:16:41 -07:00
include riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion 2021-08-06 22:41:28 -07:00
kernel riscv: stacktrace: Fix NULL pointer dereference 2021-07-24 12:58:51 -07:00
lib riscv: __asm_copy_to-from_user: Fix: Typos in comments 2021-07-23 17:49:12 -07:00
mm riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion 2021-08-06 22:41:28 -07:00
net riscv: bpf: Avoid breaking W^X 2021-04-26 08:25:14 -07:00
Kbuild
Kconfig Revert "riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED" 2021-08-06 22:41:39 -07:00
Kconfig.debug
Kconfig.erratas riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y 2021-05-06 09:40:13 -07:00
Kconfig.socs riscv: sifive: fix Kconfig errata warning 2021-06-12 17:20:50 -07:00
Makefile Kbuild updates for v5.14 2021-07-10 11:01:38 -07:00