fbaff050bb
Add the print of the CPU type and SOC revision during boot. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Robert Karszniewicz <r.karszniewicz@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/micrel_phy.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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static void __init imx6ul_enet_clk_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
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IMX6UL_GPR1_ENET_CLK_OUTPUT);
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else
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pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
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}
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static inline void imx6ul_enet_init(void)
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{
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imx6ul_enet_clk_init();
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}
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static void __init imx6ul_init_machine(void)
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{
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imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL",
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imx_get_soc_revision());
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of_platform_default_populate(NULL, NULL, NULL);
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imx6ul_enet_init();
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imx_anatop_init();
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imx6ul_pm_init();
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}
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static void __init imx6ul_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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imx6_pm_ccm_init("fsl,imx6ul-ccm");
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}
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static void __init imx6ul_init_late(void)
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{
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imx6sx_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
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platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
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}
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static const char * const imx6ul_dt_compat[] __initconst = {
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"fsl,imx6ul",
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"fsl,imx6ull",
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NULL,
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};
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DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
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.init_irq = imx6ul_init_irq,
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.init_machine = imx6ul_init_machine,
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.init_late = imx6ul_init_late,
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.dt_compat = imx6ul_dt_compat,
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MACHINE_END
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