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Commit 08ed77e414ab2342 ("perf vendor events amd: Add recommended events") added the hits event "L2 Cache Hits from L2 HWPF" with the same metric expression as the accesses event "L2 Cache Accesses from L2 HWPF": $ perf list --details ... l2_cache_accesses_from_l2_hwpf [L2 Cache Accesses from L2 HWPF] [l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3] l2_cache_hits_from_l2_hwpf [L2 Cache Hits from L2 HWPF] [l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3] ... This was wrong and led to counting hits the same as accesses. Section 2.1.15.2 "Performance Measurement" of "PPR for AMD Family 17h Model 31h B0 - 55803 Rev 0.54 - Sep 12, 2019", documents the hits event with EventCode 0x70 which is the same as l2_pf_hit_l2. Fix this, and massage the description for l2_pf_hit_l2 as the hits event is now the duplicate of l2_pf_hit_l2. AMD recommends using the recommended event over other events if the duplicate exists and maintain both for consistency. Hence, l2_cache_hits_from_l2_hwpf should override l2_pf_hit_l2. Before: # perf stat -M l2_cache_accesses_from_l2_hwpf,l2_cache_hits_from_l2_hwpf sleep 1 Performance counter stats for 'sleep 1': 1,436 l2_pf_miss_l2_l3 # 11114.00 l2_cache_accesses_from_l2_hwpf # 11114.00 l2_cache_hits_from_l2_hwpf 4,482 l2_pf_hit_l2 5,196 l2_pf_miss_l2_hit_l3 1.001765339 seconds time elapsed After: # perf stat -M l2_cache_accesses_from_l2_hwpf sleep 1 Performance counter stats for 'sleep 1': 1,477 l2_pf_miss_l2_l3 # 10442.00 l2_cache_accesses_from_l2_hwpf 3,978 l2_pf_hit_l2 4,987 l2_pf_miss_l2_hit_l3 1.001491186 seconds time elapsed # perf stat -e l2_cache_hits_from_l2_hwpf sleep 1 Performance counter stats for 'sleep 1': 3,983 l2_cache_hits_from_l2_hwpf 1.001329970 seconds time elapsed Note the difference in performance counter values for the accesses versus the hits after the fix, and the hits event now counting the same as l2_pf_hit_l2. Fixes: 08ed77e414ab ("perf vendor events amd: Add recommended events") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Robert Richter <rrichter@amd.com> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Tested-by: Arnaldo Carvalho de Melo <acme@kernel.org> # On a 3900X Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kim Phillips <kim.phillips@amd.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Martin Liška <mliska@suse.cz> Cc: Michael Petlan <mpetlan@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Vijay Thakkar <vijaythakkar@me.com> Cc: linux-perf-users@vger.kernel.org Link: https://lore.kernel.org/r/20210406215944.113332-2-Smita.KoralahalliChannabasappa@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
The contents of this directory allow users to specify PMU events in their CPUs by their symbolic names rather than raw event codes (see example below). The main program in this directory, is the 'jevents', which is built and executed _BEFORE_ the perf binary itself is built. The 'jevents' program tries to locate and process JSON files in the directory tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - The CSV file that maps a specific CPU to its set of PMU events is to be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored. - To reduce JSON event duplication per architecture, platform JSONs may use "ArchStdEvent" keyword to dereference an "Architecture standard events", defined in architecture standard JSONs. Architecture standard JSONs must be located in the architecture root folder. Matching is based on the "EventName" field. The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies the topic. Eg: "Floating-point.json". All the topic JSON files for a CPU model/family should be in a separate sub directory. Thus for the Silvermont X86 CPU: $ ls tools/perf/pmu-events/arch/x86/silvermont cache.json memory.json virtual-memory.json frontend.json pipeline.json The JSONs folder for a CPU model/family may be placed in the root arch folder, or may be placed in a vendor sub-folder under the arch folder for instances where the arch and vendor are not the same. Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: - Set of 'PMU events tables' for all known CPUs in the architecture, (one table like the following, per JSON file; table name 'pme_power8' is derived from JSON file name, 'power8.json'). struct pmu_event pme_power8[] = { ... { .name = "pm_1plus_ppc_cmpl", .event = "event=0x100f2", .desc = "1 or more ppc insts finished,", }, ... } - A 'mapping table' that maps each CPU of the architecture, to its 'PMU events table' struct pmu_events_map pmu_events_map[] = { { .cpuid = "004b0000", .version = "1", .type = "core", .table = pme_power8 }, ... }; After the 'pmu-events.c' is generated, it is compiled and the resulting 'pmu-events.o' is added to 'libperf.a' which is then used to build perf. NOTES: 1. Several CPUs can support same set of events and hence use a common JSON file. Hence several entries in the pmu_events_map[] could map to a single 'PMU events table'. 2. The 'pmu-events.h' has an extern declaration for the mapping table and the generated 'pmu-events.c' defines this table. 3. _All_ known CPU tables for architecture are included in the perf binary. At run time, perf determines the actual CPU it is running on, finds the matching events table and builds aliases for those events. This allows users to specify events by their name: $ perf stat -e pm_1plus_ppc_cmpl sleep 1 where 'pm_1plus_ppc_cmpl' is a Power8 PMU event. However some errors in processing may cause the alias build to fail. Mapfile format =============== The mapfile enables multiple CPU models to share a single set of PMU events. It is required even if such mapping is 1:1. The mapfile.csv format is expected to be: Header line CPUID,Version,Dir/path/name,Type where: Comma: is the required field delimiter (i.e other fields cannot have commas within them). Comments: Lines in which the first character is either '\n' or '#' are ignored. Header line The header line is the first line in the file, which is always _IGNORED_. It can be empty. CPUID: CPUID is an arch-specific char string, that can be used to identify CPU (and associate it with a set of PMU events it supports). Multiple CPUIDS can point to the same File/path/name.json. Example: CPUID == 'GenuineIntel-6-2E' (on x86). CPUID == '004b0100' (PVR value in Powerpc) Version: is the Version of the mapfile. Dir/path/name: is the pathname to the directory containing the CPU's JSON files, relative to the directory containing the mapfile.csv Type: indicates whether the events are "core" or "uncore" events. Eg: $ grep silvermont tools/perf/pmu-events/arch/x86/mapfile.csv GenuineIntel-6-37,v13,silvermont,core GenuineIntel-6-4D,v13,silvermont,core GenuineIntel-6-4C,v13,silvermont,core i.e the three CPU models use the JSON files (i.e PMU events) listed in the directory 'tools/perf/pmu-events/arch/x86/silvermont'.