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linux/drivers/clk/renesas
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Biju Das 86e122c075 clk: renesas: rzg2l: Add CPG_PL1_DDIV macro 
Core clock "I" is sourced from  CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19 11:34:56 +01:00
..
clk-div6.c
clk: renesas: div6: Implement range checking
2021-05-11 09:58:13 +02:00
clk-div6.h
We have two changes to the core framework this time around. The first being a
2017-11-17 20:04:24 -08:00
clk-emev2.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-mstp.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
clk-r8a73a4.c
clk: Remove io.h from clk-provider.h
2019-05-15 13:21:37 -07:00
clk-r8a7740.c
clk: Remove io.h from clk-provider.h
2019-05-15 13:21:37 -07:00
clk-r8a7778.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-r8a7779.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-rz.c
remove ioremap_nocache and devm_ioremap_nocache
2020-01-06 09:45:59 +01:00
clk-sh73a0.c
clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
2020-12-10 08:34:01 +01:00
Kconfig
clk: renesas: Make CLK_R9A06G032 invisible
2021-08-13 12:05:41 +02:00
Makefile
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
2021-07-19 11:22:20 +02:00
r7s9210-cpg-mssr.c
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a774b1-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a774c0-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a774e1-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a779a0-cpg-mssr.c
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
r8a7742-cpg-mssr.c
clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a7796-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a77470-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a77970-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77980-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a77990-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r8a77995-cpg-mssr.c
clk: renesas: rcar-gen3: Add SDnH clock
2021-11-19 11:27:58 +01:00
r9a06g032-clocks.c
clk: renesas: r9a06g032: Switch to .determine_rate()
2021-05-11 10:00:40 +02:00
r9a07g044-cpg.c
clk: renesas: r9a07g044: Add OSTM clock and reset entries
2021-11-15 10:47:18 +01:00
rcar-cpg-lib.c
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-cpg-lib.h
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c
clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
2021-11-19 11:32:39 +01:00
rcar-gen3-cpg.h
clk: renesas: rcar-gen3: Add dummy SDnH clock
2021-11-19 11:27:58 +01:00
rcar-usb2-clock-sel.c
clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference
2021-08-28 21:29:36 -07:00
renesas-cpg-mssr.c
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
2021-05-27 15:27:16 +02:00
renesas-cpg-mssr.h
clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-17 15:32:25 +02:00
rzg2l-cpg.c
clk: renesas: rzg2l: Add missing kerneldoc for resets
2021-11-15 10:00:31 +01:00
rzg2l-cpg.h
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
2021-11-19 11:34:56 +01:00