3a5b2a0883
This driver relies on either the FW (on the PF) or the PF (on the VF) to know how crypto services and rings map to one another. Store this information so that it can be referenced in the future at runtime for checks or extensions. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_pfvf_vf_msg.h>
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#include "adf_c3xxxvf_hw_data.h"
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static struct adf_hw_device_class c3xxxiov_class = {
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.name = ADF_C3XXXVF_DEVICE_NAME,
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.type = DEV_C3XXXVF,
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.instances = 0
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};
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static u32 get_accel_mask(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_ACCELERATORS_MASK;
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}
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static u32 get_ae_mask(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_ACCELENGINES_MASK;
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}
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static u32 get_num_accels(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_MAX_ACCELERATORS;
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}
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static u32 get_num_aes(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_MAX_ACCELENGINES;
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}
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static u32 get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_PMISC_BAR;
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}
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static u32 get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_C3XXXIOV_ETR_BAR;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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return DEV_SKU_VF;
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}
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static int adf_vf_int_noop(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static void adf_vf_void_noop(struct adf_accel_dev *accel_dev)
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{
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}
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void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &c3xxxiov_class;
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hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;
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hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
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hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS;
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hw_data->num_logical_accel = 1;
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hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;
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hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_vf_isr_resource_alloc;
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hw_data->free_irq = adf_vf_isr_resource_free;
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hw_data->enable_error_correction = adf_vf_void_noop;
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hw_data->init_admin_comms = adf_vf_int_noop;
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hw_data->exit_admin_comms = adf_vf_void_noop;
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hw_data->send_admin_init = adf_vf2pf_notify_init;
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hw_data->init_arb = adf_vf_int_noop;
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hw_data->exit_arb = adf_vf_void_noop;
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hw_data->disable_iov = adf_vf2pf_notify_shutdown;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_num_accels = get_num_accels;
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->dev_class->instances++;
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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adf_devmgr_update_class_index(hw_data);
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}
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