77a618b148
CONFIG_QCOM_A7PLL is tristate option and therefore this driver can be
compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
Fixes: 5a5223ffd7 ("clk: qcom: Add A7 PLL support")
Signed-off-by: Chen Hui <clare.chenhui@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210409082352.233810-2-clare.chenhui@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm A7 PLL driver
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*
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* Copyright (c) 2020, Linaro Limited
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-alpha-pll.h"
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#define LUCID_PLL_OFF_L_VAL 0x04
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static const struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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static struct clk_alpha_pll a7pll = {
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.offset = 0x100,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "a7pll",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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static const struct alpha_pll_config a7pll_config = {
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.l = 0x39,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x2261,
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.config_ctl_hi1_val = 0x029A699C,
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.user_ctl_val = 0x1,
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.user_ctl_hi_val = 0x805,
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};
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static const struct regmap_config a7pll_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x1000,
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.fast_io = true,
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};
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static int qcom_a7pll_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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void __iomem *base;
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u32 l_val;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Configure PLL only if the l_val is zero */
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regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
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if (!l_val)
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clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
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ret = devm_clk_register_regmap(dev, &a7pll.clkr);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&a7pll.clkr.hw);
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}
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static const struct of_device_id qcom_a7pll_match_table[] = {
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{ .compatible = "qcom,sdx55-a7pll" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
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static struct platform_driver qcom_a7pll_driver = {
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.probe = qcom_a7pll_probe,
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.driver = {
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.name = "qcom-a7pll",
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.of_match_table = qcom_a7pll_match_table,
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},
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};
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module_platform_driver(qcom_a7pll_driver);
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MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
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MODULE_LICENSE("GPL v2");
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