8940ac9ced
As part of the GHCB specification, the booting of APs under SEV-ES
requires an AP jump table when transitioning from one layer of code to
another (e.g. when going from UEFI to the OS). As a result, each layer
that parks an AP must provide the physical address of an AP jump table
to the next layer via the hypervisor.
Upon booting of the kernel, read the AP jump table address from the
hypervisor. Under SEV-ES, APs are started using the INIT-SIPI-SIPI
sequence. Before issuing the first SIPI request for an AP, the start
CS and IP is programmed into the AP jump table. Upon issuing the SIPI
request, the AP will awaken and jump to that start CS:IP address.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
[ jroedel@suse.de: - Adapted to different code base
- Moved AP table setup from SIPI sending path to
real-mode setup code
- Fix sparse warnings ]
Co-developed-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200907131613.12703-67-joro@8bytes.org
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Encrypted Register State Support
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*
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef __ASM_ENCRYPTED_STATE_H
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#define __ASM_ENCRYPTED_STATE_H
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#include <linux/types.h>
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#include <asm/insn.h>
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#define GHCB_SEV_INFO 0x001UL
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#define GHCB_SEV_INFO_REQ 0x002UL
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#define GHCB_INFO(v) ((v) & 0xfffUL)
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#define GHCB_PROTO_MAX(v) (((v) >> 48) & 0xffffUL)
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#define GHCB_PROTO_MIN(v) (((v) >> 32) & 0xffffUL)
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#define GHCB_PROTO_OUR 0x0001UL
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#define GHCB_SEV_CPUID_REQ 0x004UL
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#define GHCB_CPUID_REQ_EAX 0
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#define GHCB_CPUID_REQ_EBX 1
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#define GHCB_CPUID_REQ_ECX 2
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#define GHCB_CPUID_REQ_EDX 3
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#define GHCB_CPUID_REQ(fn, reg) (GHCB_SEV_CPUID_REQ | \
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(((unsigned long)reg & 3) << 30) | \
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(((unsigned long)fn) << 32))
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#define GHCB_PROTOCOL_MAX 0x0001UL
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#define GHCB_DEFAULT_USAGE 0x0000UL
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#define GHCB_SEV_CPUID_RESP 0x005UL
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#define GHCB_SEV_TERMINATE 0x100UL
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#define GHCB_SEV_TERMINATE_REASON(reason_set, reason_val) \
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(((((u64)reason_set) & 0x7) << 12) | \
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((((u64)reason_val) & 0xff) << 16))
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#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
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#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
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#define GHCB_SEV_GHCB_RESP_CODE(v) ((v) & 0xfff)
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#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); }
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enum es_result {
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ES_OK, /* All good */
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ES_UNSUPPORTED, /* Requested operation not supported */
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ES_VMM_ERROR, /* Unexpected state from the VMM */
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ES_DECODE_FAILED, /* Instruction decoding failed */
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ES_EXCEPTION, /* Instruction caused exception */
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ES_RETRY, /* Retry instruction emulation */
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};
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struct es_fault_info {
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unsigned long vector;
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unsigned long error_code;
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unsigned long cr2;
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};
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struct pt_regs;
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/* ES instruction emulation context */
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struct es_em_ctxt {
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struct pt_regs *regs;
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struct insn insn;
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struct es_fault_info fi;
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};
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void do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code);
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static inline u64 lower_bits(u64 val, unsigned int bits)
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{
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u64 mask = (1ULL << bits) - 1;
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return (val & mask);
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}
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struct real_mode_header;
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enum stack_type;
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/* Early IDT entry points for #VC handler */
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extern void vc_no_ghcb(void);
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extern void vc_boot_ghcb(void);
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extern bool handle_vc_boot_ghcb(struct pt_regs *regs);
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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extern struct static_key_false sev_es_enable_key;
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extern void __sev_es_ist_enter(struct pt_regs *regs);
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extern void __sev_es_ist_exit(void);
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static __always_inline void sev_es_ist_enter(struct pt_regs *regs)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_enter(regs);
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}
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static __always_inline void sev_es_ist_exit(void)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_exit();
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}
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extern int sev_es_setup_ap_jump_table(struct real_mode_header *rmh);
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#else
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static inline void sev_es_ist_enter(struct pt_regs *regs) { }
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static inline void sev_es_ist_exit(void) { }
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static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; }
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#endif
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#endif
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