Fabrice Gasnier 89d1f72570 iio: adc: stm32-adc: adapt clock duty cycle for proper operation
For proper operation, STM32 ADC should be used with a clock duty cycle
of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
can be used in case clock duty cycle is out of this range.
In case clk_get_scaled_duty_cycle() returns an error, kindly apply a
divider by default (don't make the probe fail).

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Link: https://lore.kernel.org/r/1604681846-31234-1-git-send-email-fabrice.gasnier@st.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-14 15:51:13 +00:00
..
2020-09-29 17:34:25 +01:00
2020-07-20 09:37:31 +02:00
2020-11-01 15:31:56 +00:00
2020-09-14 06:57:52 +02:00