05c47036c6
This document is almost in ReST format. The only thing needed is to mark a list as such and to add an extra whitespace. Yet, let's also use the standard document title markup, as it makes easier if anyone wants later to add sessions to it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
59 lines
2.1 KiB
ReStructuredText
59 lines
2.1 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=========================
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MPIC interrupt controller
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=========================
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Device types supported:
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- KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
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- KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
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Only one MPIC instance, of any type, may be instantiated. The created
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MPIC will act as the system interrupt controller, connecting to each
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vcpu's interrupt inputs.
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Groups:
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KVM_DEV_MPIC_GRP_MISC
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Attributes:
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KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
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Base address of the 256 KiB MPIC register space. Must be
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naturally aligned. A value of zero disables the mapping.
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Reset value is zero.
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KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
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Access an MPIC register, as if the access were made from the guest.
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"attr" is the byte offset into the MPIC register space. Accesses
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must be 4-byte aligned.
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MSIs may be signaled by using this attribute group to write
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to the relevant MSIIR.
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KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
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IRQ input line for each standard openpic source. 0 is inactive and 1
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is active, regardless of interrupt sense.
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For edge-triggered interrupts: Writing 1 is considered an activating
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edge, and writing 0 is ignored. Reading returns 1 if a previously
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signaled edge has not been acknowledged, and 0 otherwise.
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"attr" is the IRQ number. IRQ numbers for standard sources are the
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byte offset of the relevant IVPR from EIVPR0, divided by 32.
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IRQ Routing:
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The MPIC emulation supports IRQ routing. Only a single MPIC device can
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be instantiated. Once that device has been created, it's available as
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irqchip id 0.
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This irqchip 0 has 256 interrupt pins, which expose the interrupts in
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the main array of interrupt sources (a.k.a. "SRC" interrupts).
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The numbering is the same as the MPIC device tree binding -- based on
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the register offset from the beginning of the sources array, without
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regard to any subdivisions in chip documentation such as "internal"
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or "external" interrupts.
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Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
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