a57066b1a0
The UDP reuseport conflict was a little bit tricky. The net-next code, via bpf-next, extracted the reuseport handling into a helper so that the BPF sk lookup code could invoke it. At the same time, the logic for reuseport handling of unconnected sockets changed via commit efc6b6f6c3113e8b203b9debfb72d81e0f3dcace which changed the logic to carry on the reuseport result into the rest of the lookup loop if we do not return immediately. This requires moving the reuseport_has_conns() logic into the callers. While we are here, get rid of inline directives as they do not belong in foo.c files. The other changes were cases of more straightforward overlapping modifications. Signed-off-by: David S. Miller <davem@davemloft.net>
397 lines
9.9 KiB
C
397 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Atlantic Network Driver
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*
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* Copyright (C) 2014-2019 aQuantia Corporation
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* Copyright (C) 2019-2020 Marvell International Ltd.
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*/
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/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific
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* functions.
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*/
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#ifndef AQ_HW_H
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#define AQ_HW_H
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#include "aq_common.h"
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#include "aq_rss.h"
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#include "hw_atl/hw_atl_utils.h"
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#define AQ_HW_MAC_COUNTER_HZ 312500000ll
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#define AQ_HW_PHY_COUNTER_HZ 160000000ll
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enum aq_tc_mode {
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AQ_TC_MODE_INVALID = -1,
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AQ_TC_MODE_8TCS,
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AQ_TC_MODE_4TCS,
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};
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#define AQ_RX_FIRST_LOC_FVLANID 0U
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#define AQ_RX_LAST_LOC_FVLANID 15U
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#define AQ_RX_FIRST_LOC_FETHERT 16U
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#define AQ_RX_LAST_LOC_FETHERT 31U
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#define AQ_RX_FIRST_LOC_FL3L4 32U
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#define AQ_RX_LAST_LOC_FL3L4 39U
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#define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4
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#define AQ_VLAN_MAX_FILTERS \
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(AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
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#define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU
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#define AQ_FRAC_PER_NS 0x100000000LL
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/* Used for rate to Mbps conversion */
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#define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */
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/* NIC H/W capabilities */
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struct aq_hw_caps_s {
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u64 hw_features;
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u64 link_speed_msk;
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unsigned int hw_priv_flags;
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u32 media_type;
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u32 rxds_max;
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u32 txds_max;
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u32 rxds_min;
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u32 txds_min;
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u32 txhwb_alignment;
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u32 irq_mask;
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u32 vecs;
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u32 mtu;
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u32 mac_regs_count;
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u32 hw_alive_check_addr;
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u8 msix_irqs;
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u8 tcs_max;
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u8 rxd_alignment;
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u8 rxd_size;
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u8 txd_alignment;
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u8 txd_size;
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u8 tx_rings;
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u8 rx_rings;
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bool flow_control;
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bool is_64_dma;
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bool op64bit;
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u32 quirks;
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u32 priv_data_len;
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};
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struct aq_hw_link_status_s {
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unsigned int mbps;
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bool full_duplex;
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u32 lp_link_speed_msk;
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u32 lp_flow_control;
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};
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struct aq_stats_s {
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u64 uprc;
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u64 mprc;
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u64 bprc;
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u64 erpt;
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u64 uptc;
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u64 mptc;
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u64 bptc;
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u64 erpr;
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u64 mbtc;
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u64 bbtc;
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u64 mbrc;
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u64 bbrc;
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u64 ubrc;
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u64 ubtc;
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u64 dpc;
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u64 dma_pkt_rc;
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u64 dma_pkt_tc;
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u64 dma_oct_rc;
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u64 dma_oct_tc;
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};
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#define AQ_HW_IRQ_INVALID 0U
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#define AQ_HW_IRQ_LEGACY 1U
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#define AQ_HW_IRQ_MSI 2U
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#define AQ_HW_IRQ_MSIX 3U
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#define AQ_HW_SERVICE_IRQS 1U
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#define AQ_HW_POWER_STATE_D0 0U
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#define AQ_HW_POWER_STATE_D3 3U
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#define AQ_HW_FLAG_STARTED 0x00000004U
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#define AQ_HW_FLAG_STOPPING 0x00000008U
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#define AQ_HW_FLAG_RESETTING 0x00000010U
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#define AQ_HW_FLAG_CLOSING 0x00000020U
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#define AQ_HW_PTP_AVAILABLE 0x01000000U
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#define AQ_HW_LINK_DOWN 0x04000000U
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#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U
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#define AQ_HW_FLAG_ERR_HW 0x80000000U
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#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
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#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
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AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
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AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
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#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
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AQ_NIC_LINK_DOWN)
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#define AQ_HW_MEDIA_TYPE_TP 1U
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#define AQ_HW_MEDIA_TYPE_FIBRE 2U
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#define AQ_HW_TXD_MULTIPLE 8U
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#define AQ_HW_RXD_MULTIPLE 8U
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#define AQ_HW_QUEUES_MAX 32U
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#define AQ_HW_MULTICAST_ADDRESS_MAX 32U
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#define AQ_HW_PTP_TC 2U
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#define AQ_HW_LED_BLINK 0x2U
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#define AQ_HW_LED_DEFAULT 0x0U
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enum aq_priv_flags {
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AQ_HW_LOOPBACK_DMA_SYS,
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AQ_HW_LOOPBACK_PKT_SYS,
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AQ_HW_LOOPBACK_DMA_NET,
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AQ_HW_LOOPBACK_PHYINT_SYS,
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AQ_HW_LOOPBACK_PHYEXT_SYS,
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};
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#define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\
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BIT(AQ_HW_LOOPBACK_PKT_SYS) |\
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BIT(AQ_HW_LOOPBACK_DMA_NET) |\
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BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\
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BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))
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#define ATL_HW_CHIP_MIPS 0x00000001U
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#define ATL_HW_CHIP_TPO2 0x00000002U
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#define ATL_HW_CHIP_RPF2 0x00000004U
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#define ATL_HW_CHIP_MPI_AQ 0x00000010U
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#define ATL_HW_CHIP_ATLANTIC 0x00800000U
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#define ATL_HW_CHIP_REVISION_A0 0x01000000U
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#define ATL_HW_CHIP_REVISION_B0 0x02000000U
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#define ATL_HW_CHIP_REVISION_B1 0x04000000U
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#define ATL_HW_CHIP_ANTIGUA 0x08000000U
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#define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \
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(_HW_)->chip_features))
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struct aq_hw_s {
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atomic_t flags;
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u8 rbl_enabled:1;
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struct aq_nic_cfg_s *aq_nic_cfg;
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const struct aq_fw_ops *aq_fw_ops;
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void __iomem *mmio;
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struct aq_hw_link_status_s aq_link_status;
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struct hw_atl_utils_mbox mbox;
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struct hw_atl_stats_s last_stats;
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struct aq_stats_s curr_stats;
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u64 speed;
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u32 itr_tx;
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u32 itr_rx;
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unsigned int chip_features;
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u32 fw_ver_actual;
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atomic_t dpc;
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u32 mbox_addr;
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u32 rpc_addr;
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u32 settings_addr;
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u32 rpc_tid;
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struct hw_atl_utils_fw_rpc rpc;
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s64 ptp_clk_offset;
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u16 phy_id;
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void *priv;
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};
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struct aq_ring_s;
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struct aq_ring_param_s;
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struct sk_buff;
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struct aq_rx_filter_l3l4;
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struct aq_hw_ops {
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int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
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unsigned int frags);
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int (*hw_ring_rx_receive)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
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unsigned int sw_tail_old);
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int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
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int (*hw_soft_reset)(struct aq_hw_s *self);
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int (*hw_prepare)(struct aq_hw_s *self,
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const struct aq_fw_ops **fw_ops);
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int (*hw_reset)(struct aq_hw_s *self);
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int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr);
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int (*hw_start)(struct aq_hw_s *self);
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int (*hw_stop)(struct aq_hw_s *self);
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int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
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struct aq_ring_param_s *aq_ring_param);
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int (*hw_ring_tx_start)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_ring_tx_stop)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_ring_rx_init)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring,
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struct aq_ring_param_s *aq_ring_param);
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int (*hw_ring_rx_start)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_ring_rx_stop)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);
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int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);
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int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);
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int (*hw_packet_filter_set)(struct aq_hw_s *self,
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unsigned int packet_filter);
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int (*hw_filter_l3l4_set)(struct aq_hw_s *self,
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struct aq_rx_filter_l3l4 *data);
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int (*hw_filter_l3l4_clear)(struct aq_hw_s *self,
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struct aq_rx_filter_l3l4 *data);
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int (*hw_filter_l2_set)(struct aq_hw_s *self,
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struct aq_rx_filter_l2 *data);
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int (*hw_filter_l2_clear)(struct aq_hw_s *self,
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struct aq_rx_filter_l2 *data);
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int (*hw_filter_vlan_set)(struct aq_hw_s *self,
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struct aq_rx_filter_vlan *aq_vlans);
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int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable);
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int (*hw_multicast_list_set)(struct aq_hw_s *self,
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u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]
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[ETH_ALEN],
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u32 count);
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int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);
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int (*hw_rss_set)(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params);
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int (*hw_rss_hash_set)(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params);
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int (*hw_tc_rate_limit_set)(struct aq_hw_s *self);
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int (*hw_get_regs)(struct aq_hw_s *self,
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const struct aq_hw_caps_s *aq_hw_caps,
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u32 *regs_buff);
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struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);
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u32 (*hw_get_fw_version)(struct aq_hw_s *self);
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int (*hw_set_offload)(struct aq_hw_s *self,
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struct aq_nic_cfg_s *aq_nic_cfg);
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int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring);
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int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self,
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struct aq_ring_s *ring);
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void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp);
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int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta);
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int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta);
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int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts);
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int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time);
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int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start,
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u32 period);
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int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index,
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u32 enable);
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int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts);
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u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len,
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u64 *timestamp);
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int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len,
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u64 *timestamp);
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int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);
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int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);
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int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp);
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};
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struct aq_fw_ops {
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int (*init)(struct aq_hw_s *self);
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int (*deinit)(struct aq_hw_s *self);
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int (*reset)(struct aq_hw_s *self);
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int (*renegotiate)(struct aq_hw_s *self);
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int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);
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int (*set_link_speed)(struct aq_hw_s *self, u32 speed);
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int (*set_state)(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state);
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int (*update_link_status)(struct aq_hw_s *self);
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int (*update_stats)(struct aq_hw_s *self);
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int (*get_mac_temp)(struct aq_hw_s *self, int *temp);
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int (*get_phy_temp)(struct aq_hw_s *self, int *temp);
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u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode);
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int (*set_flow_control)(struct aq_hw_s *self);
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int (*led_control)(struct aq_hw_s *self, u32 mode);
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int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);
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int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
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u8 *mac);
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int (*send_fw_request)(struct aq_hw_s *self,
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const struct hw_fw_request_iface *fw_req,
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size_t size);
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void (*enable_ptp)(struct aq_hw_s *self, int enable);
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void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj);
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int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);
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int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,
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u32 *supported_rates);
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u32 (*get_link_capabilities)(struct aq_hw_s *self);
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int (*send_macsec_req)(struct aq_hw_s *self,
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struct macsec_msg_fw_request *msg,
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struct macsec_msg_fw_response *resp);
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};
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#endif /* AQ_HW_H */
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