6e2bdf7dc3
The "data" region of the PolarFire SoC's system controller mailbox is
not one continuous register space - the system controller's QSPI sits
between the control and data registers. Split the "data" reg into two
parts: "data" & "control".
Fixes: 213556235526 ("dt-bindings: soc/microchip: update syscontroller compatibles")
Fixes: ed9543d6f2c4 ("dt-bindings: add bindings for polarfire soc mailbox")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
55 lines
1.3 KiB
YAML
55 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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properties:
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compatible:
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const: microchip,mpfs-mailbox
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reg:
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oneOf:
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- items:
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- description: mailbox control & data registers
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- description: mailbox interrupt registers
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deprecated: true
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- items:
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- description: mailbox control registers
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- description: mailbox interrupt registers
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- description: mailbox data registers
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mbox: mailbox@37020000 {
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compatible = "microchip,mpfs-mailbox";
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reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
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<0x0 0x37020800 0x0 0x100>;
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interrupt-parent = <&L1>;
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interrupts = <96>;
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#mbox-cells = <1>;
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};
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};
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