Vikas Sajjan 8bc2eeb83e clk: samsung: Reorder MUX registration for mout_vpllsrc ...

While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
"fout_vpll" (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2013-08-02 13:22:28 -07:00

..

clk-exynos4.c

clk: samsung: Add support to register rate_table for samsung plls

2013-08-02 13:22:09 -07:00

clk-exynos5250.c

clk: samsung: Reorder MUX registration for mout_vpllsrc

2013-08-02 13:22:28 -07:00

clk-exynos5420.c

clk: samsung: Add support to register rate_table for samsung plls

2013-08-02 13:22:09 -07:00

clk-exynos5440.c

clk: exynos5440: Staticize local symbols

2013-07-25 14:18:36 -07:00

clk-exynos-audss.c

clk: exynos-audss: Staticize exynos_audss_clk_init

2013-07-25 14:18:40 -07:00

clk-pll.c

clk: samsung: Add set_rate() clk_ops for PLL36xx

2013-08-02 13:22:10 -07:00

clk-pll.h

clk: samsung: Add support to register rate_table for samsung plls

2013-08-02 13:22:09 -07:00

clk.c

clk: samsung: Fix compilation error

2013-04-08 23:43:12 +09:00

clk.h

clk: samsung: Add support to register rate_table for samsung plls

2013-08-02 13:22:09 -07:00

Makefile

clk: exynos5420: register clocks using common clock framework

2013-06-19 04:09:34 +09:00