8bf0a8048b
When Priority Mask Hint Enable (PMHE) == 0b1, the GIC may use the PMR
value to determine whether to signal an IRQ to a PE, and consequently
after a change to the PMR value, a DSB SY may be required to ensure that
interrupts are signalled to a CPU in finite time. When PMHE == 0b0,
interrupts are always signalled to the relevant PE, and all masking
occurs locally, without requiring a DSB SY.
Since commit:
f226650494c6aa87 ("arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear")
... we handle this dynamically: in most cases a static key is used to
determine whether to issue a DSB SY, but the entry code must read from
ICC_CTLR_EL1 as static keys aren't accessible from plain assembly.
It would be much nicer to use an alternative instruction sequence for
the DSB, as this would avoid the need to read from ICC_CTLR_EL1 in the
entry code, and for most other code this will result in simpler code
generation with fewer instructions and fewer branches.
This patch adds a new ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap which is
only set when ICC_CTLR_EL1.PMHE == 0b0 (and GIC priority masking is in
use). This allows us to replace the existing users of the
`gic_pmr_sync` static key with alternative sequences which default to a
DSB SY and are relaxed to a NOP when PMHE is not in use.
The entry assembly management of the PMR is slightly restructured to use
a branch (rather than multiple NOPs) when priority masking is not in
use. This is more in keeping with other alternatives in the entry
assembly, and permits the use of a separate alternatives for the
PMHE-dependent DSB SY (and removal of the conditional branch this
currently requires). For consistency I've adjusted both the save and
restore paths.
According to bloat-o-meter, when building defconfig +
CONFIG_ARM64_PSEUDO_NMI=y this shrinks the kernel text by ~4KiB:
| add/remove: 4/2 grow/shrink: 42/310 up/down: 332/-5032 (-4700)
The resulting vmlinux is ~66KiB smaller, though the resulting Image size
is unchanged due to padding and alignment:
| [mark@lakrids:~/src/linux]% ls -al vmlinux-*
| -rwxr-xr-x 1 mark mark 137508344 Jan 17 14:11 vmlinux-after
| -rwxr-xr-x 1 mark mark 137575440 Jan 17 13:49 vmlinux-before
| [mark@lakrids:~/src/linux]% ls -al Image-*
| -rw-r--r-- 1 mark mark 38777344 Jan 17 14:11 Image-after
| -rw-r--r-- 1 mark mark 38777344 Jan 17 13:49 Image-before
Prior to this patch we did not verify the state of ICC_CTLR_EL1.PMHE on
secondary CPUs. As of this patch this is verified by the cpufeature code
when using GIC priority masking (i.e. when using pseudo-NMIs).
Note that since commit:
7e3a57fa6ca831fa ("arm64: Document ICC_CTLR_EL3.PMHE setting requirements")
... Documentation/arm64/booting.rst specifies:
| - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
| all CPUs the kernel is executing on, and must stay constant
| for the lifetime of the kernel.
... so that should not adversely affect any compliant systems, and as
we'll only check for the absense of PMHE when using pseudo-NMIs, this
will only fire when such mismatch will adversely affect the system.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20230130145429.903791-5-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Linker script variables to be set after section resolution, as
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* ld.lld does not like variables assigned before SECTIONS is processed.
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*/
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#ifndef __ARM64_KERNEL_IMAGE_VARS_H
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#define __ARM64_KERNEL_IMAGE_VARS_H
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#ifndef LINKER_SCRIPT
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#error This file should only be included in vmlinux.lds.S
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#endif
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PROVIDE(__efistub_primary_entry_offset = primary_entry - _text);
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/*
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* The EFI stub has its own symbol namespace prefixed by __efistub_, to
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* isolate it from the kernel proper. The following symbols are legally
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* accessed by the stub, so provide some aliases to make them accessible.
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* Only include data symbols here, or text symbols of functions that are
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* guaranteed to be safe when executed at another offset than they were
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* linked at. The routines below are all implemented in assembler in a
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* position independent manner
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*/
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PROVIDE(__efistub_dcache_clean_poc = __pi_dcache_clean_poc);
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PROVIDE(__efistub__text = _text);
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PROVIDE(__efistub__end = _end);
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PROVIDE(__efistub__edata = _edata);
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PROVIDE(__efistub_screen_info = screen_info);
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PROVIDE(__efistub__ctype = _ctype);
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PROVIDE(__pi___memcpy = __pi_memcpy);
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PROVIDE(__pi___memmove = __pi_memmove);
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PROVIDE(__pi___memset = __pi_memset);
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#ifdef CONFIG_KVM
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/*
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* KVM nVHE code has its own symbol namespace prefixed with __kvm_nvhe_, to
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* separate it from the kernel proper. The following symbols are legally
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* accessed by it, therefore provide aliases to make them linkable.
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* Do not include symbols which may not be safely accessed under hypervisor
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* memory mappings.
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*/
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/* Alternative callbacks for init-time patching of nVHE hyp code. */
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KVM_NVHE_ALIAS(kvm_patch_vector_branch);
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KVM_NVHE_ALIAS(kvm_update_va_mask);
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KVM_NVHE_ALIAS(kvm_get_kimage_voffset);
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KVM_NVHE_ALIAS(kvm_compute_final_ctr_el0);
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KVM_NVHE_ALIAS(spectre_bhb_patch_loop_iter);
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KVM_NVHE_ALIAS(spectre_bhb_patch_loop_mitigation_enable);
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KVM_NVHE_ALIAS(spectre_bhb_patch_wa3);
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KVM_NVHE_ALIAS(spectre_bhb_patch_clearbhb);
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KVM_NVHE_ALIAS(alt_cb_patch_nops);
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/* Global kernel state accessed by nVHE hyp code. */
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KVM_NVHE_ALIAS(kvm_vgic_global_state);
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/* Kernel symbols used to call panic() from nVHE hyp code (via ERET). */
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KVM_NVHE_ALIAS(nvhe_hyp_panic_handler);
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/* Vectors installed by hyp-init on reset HVC. */
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KVM_NVHE_ALIAS(__hyp_stub_vectors);
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/* Static keys which are set if a vGIC trap should be handled in hyp. */
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KVM_NVHE_ALIAS(vgic_v2_cpuif_trap);
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KVM_NVHE_ALIAS(vgic_v3_cpuif_trap);
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#ifdef CONFIG_ARM64_PSEUDO_NMI
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/* Static key checked in GIC_PRIO_IRQOFF. */
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KVM_NVHE_ALIAS(gic_nonsecure_priorities);
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#endif
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/* EL2 exception handling */
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KVM_NVHE_ALIAS(__start___kvm_ex_table);
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KVM_NVHE_ALIAS(__stop___kvm_ex_table);
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/* PMU available static key */
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#ifdef CONFIG_HW_PERF_EVENTS
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KVM_NVHE_ALIAS(kvm_arm_pmu_available);
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#endif
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/* Position-independent library routines */
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KVM_NVHE_ALIAS_HYP(clear_page, __pi_clear_page);
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KVM_NVHE_ALIAS_HYP(copy_page, __pi_copy_page);
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KVM_NVHE_ALIAS_HYP(memcpy, __pi_memcpy);
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KVM_NVHE_ALIAS_HYP(memset, __pi_memset);
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#ifdef CONFIG_KASAN
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KVM_NVHE_ALIAS_HYP(__memcpy, __pi_memcpy);
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KVM_NVHE_ALIAS_HYP(__memset, __pi_memset);
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#endif
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/* Hyp memory sections */
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KVM_NVHE_ALIAS(__hyp_idmap_text_start);
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KVM_NVHE_ALIAS(__hyp_idmap_text_end);
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KVM_NVHE_ALIAS(__hyp_text_start);
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KVM_NVHE_ALIAS(__hyp_text_end);
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KVM_NVHE_ALIAS(__hyp_bss_start);
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KVM_NVHE_ALIAS(__hyp_bss_end);
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KVM_NVHE_ALIAS(__hyp_rodata_start);
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KVM_NVHE_ALIAS(__hyp_rodata_end);
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/* pKVM static key */
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KVM_NVHE_ALIAS(kvm_protected_mode_initialized);
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#endif /* CONFIG_KVM */
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#endif /* __ARM64_KERNEL_IMAGE_VARS_H */
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